CMOS SDRAM
SDRAM 256Mb E-die (x4, x8, x16)
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
AC input levels (Vih/Vil)
Value
2.4/0.4
1.4
Unit
V
Input timing measurement reference level
Input rise and fall time
V
tr/tf = 1/1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Fig. 2
3.3V
Vtt = 1.4V
1200Ω
50Ω
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Z0 = 50Ω
Output
Output
50pF
50pF
870Ω
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
Unit
Note
60
75
15
20
20
45
Row active to row active delay
RAS to CAS delay
tRRD(min)
tRCD(min)
tRP(min)
12
18
18
42
ns
ns
ns
ns
us
1
1
1
1
Row precharge time
tRAS(min)
tRAS(max)
Row active time
Row cycle time
100
65
tRC(min)
60
ns
1
Last data in to row precharge
Last data in to Active delay
tRDL(min)
tDAL(min)
tCDL(min)
tBDL(min)
tCCD(min)
2
CLK
-
2, 5
5
2 CLK + tRP
Last data in to new col. address delay
Last data in to burst stop
1
1
1
2
CLK
CLK
CLK
2
2
Col. address to col. address delay
3
CAS latency=3
CAS latency=2
Number of valid output data
ea
4
-
1
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
Rev. 1.3 August 2004
SAMSUNG [ SAMSUNG ]
