CMOS SDRAM
SDRAM 256Mb E-die (x4, x8, x16)
PIN CONFIGURATION (Top view)
x8
x4
x4
x8
x16
x16
VDD
VDD
VDD
1
2
3
4
5
6
7
8
9
10
VSS
VSS
VSS
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
WE
CAS
RAS
CS
BA0
BA1
DQ0
VDDQ
N.C
DQ1
VSSQ
N.C
DQ2
VDDQ
N.C
DQ3
VSSQ
N.C
VDD
N.C
WE
CAS
RAS
CS
BA0
BA1
N.C
VDDQ
N.C
DQ0
VSSQ
N.C
N.C
VDDQ
N.C
N.C
VSSQ
N.C
DQ3
VDDQ
N.C
N.C
VSSQ
N.C
DQ2
VDDQ
N.C
DQ7
VSSQ
N.C
DQ6
VDDQ
N.C
DQ5
VSSQ
N.C
DQ4
VDDQ
N.C
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
DQ1 11
VSSQ
N.C
VDD
N.C
WE 16
CAS 17
RAS 18
CS 19
12
13
14
15
VDDQ
DQ8
VSS
VSS
VSS
N.C/RFU N.C/RFU N.C/RFU
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
BA0 20
BA1 21
A10/AP A10/AP A10/AP 22
A0
A1
A2
A3
VDD
A0
A1
A2
A3
VDD
A0 23
A1 24
A2 25
A3 26
54Pin TSOP
(400mil x 875mil)
(0.8 mm Pin pitch)
A4
VSS
A4
VSS
A4
VSS
VDD
27
PIN FUNCTION DESCRIPTION
Pin
Name
System clock
Input Function
Active on the positive going edge to sample all inputs.
CLK
CS
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Chip select
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE
Clock enable
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12,
A0 ~ A12
Address
Column address : (x4 : CA0 ~ CA9,CA11), (x8 : CA0 ~ CA9), (x16 : CA0 ~ CA8)
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
BA0 ~ BA1
RAS
Bank select address
Row address strobe
Column address strobe
Write enable
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
CAS
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
WE
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
DQM
Data input/output mask
Data inputs/outputs are multiplexed on the same pins.
(x4 : DQ0 ~ 3), (x8 : DQ0 ~ 7), (x16 : DQ0 ~ 15)
DQ0 ~ N
Data input/output
VDD/VSS
VDDQ/VSSQ
Power supply/ground
Data output power/ground
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
No connection
/reserved for future use
N.C/RFU
This pin is recommended to be left No Connection on the device.
Rev. 1.3 August 2004
SAMSUNG [ SAMSUNG ]
