256M GDDR3 SDRAM
K4J55323QG
PROGRAMMABLE IMPEDANCE OUTPUT BUFFER AND ACTIVE TERMINATOR
The GDDR3 SDRAM is equipped with programmable impedance output buffers and Active Terminators. This allows a user to match
the driver impedance to the system. To adjust the impedance, an external precision resistor(RQ) is connected between the ZQ pin and
Vss. The value of the resistor must be six times of the desired output impedance.
For example, a 240Ω resistor is required for an output impedance of 40 Ω. To ensure that output impedance is one sixth the value of RQ
(within 10 %), the range of RQ is 120Ω to 360Ω (20Ω to 60Ω) output impedance.
MF,SEN, RES, CK and /CK are not internally terminated. CK and /CK will be terminated on the system module using external 1%
resisters. The output impedance is updated during all AUTO REFRESH commands and NOP commands when a READ is not in
progress to compensate for variations in voltage supply and temperature. The output impedance updates are transparent to the system.
Impedance updates do not affect device operation, and all data sheet timing and current specifications are met during update. To guar-
antee optimum output driver impedance after power-up, the GDDR3(x32) needs at least 20us after the clock is applied and stable to cal-
ibrate the impedance upon power-up. The user may operate the part with less than 20us, but the optimal output impedance is not
guaranteed. The value of ZQ is also used to calibrated the internal address/command termination resisters. The two termination values
that are selectable during power up are 1/2 of ZQ and ZQ. The value of ZQ is used to calibrate the internal DQ termination resisters. The
two termination values that are selectable are 1/4 of ZQ and 1/2 of ZQ.
BURST LENGTH
Read and write accesses to the GDDR3 SDRAM are burst oriented, with the burst length being programmable, as shown in MRS
table. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE com-
mand. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or
WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place
within the block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A2-Ai when
the burst length is set to four (Where Ai is the most significant column address bit for a given configuration). The remaining (least signif-
icant) address bit(s) is (are) used to select the starting location within the block. The programmable burst length applies to both READ
and WRITE bursts.
BURST TYPE
Accesses within a given burst must be programmed to be sequential; this is referred to as the burst type and is selected via bit M3.
This device does not support the interleaved burst mode found in GDDR SDRAM devices. The ordering of accesses within a burst is
determined by the burst length, the burst type, and the starting column address, as shown in below table: Burst Definition
Burst Definition
Order of Accesses
Burst
Within a Burst
Starting Column Address
Length
Type= Sequential
A2
0
A2
0
A1
0
A1
0
A0
4
0
A0
0
0 - 1 - 2 - 3
8
0 - 1 - 2 - 3 - 4 - 5 - 6 - 7
4 - 5 - 6 - 7 - 0 - 1 - 2 - 3
1
0
0
Note : 1. For a burst length of four, A2-A7 select the block of four burst; A0-A1 select the starting column within the block and must be set to zero
2. For a burst length of eight, A3-A7 select the block of eight burst; A0-A2 select the starting column within the block.
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Rev. 1.1 November 2005
SAMSUNG [ SAMSUNG ]
