256M GDDR3 SDRAM
K4J55323QG
7.2 INITIALIZATION
GDDR3 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than
those specified may result in undefined operation.
1. Apply power and keep CKE/RESET at low state ( All other inputs may be undefined)
- Apply VDD and VDDQ simultaneously
- Apply VDDQ before Vref. ( Inputs are not recognized as valid until after VREF is applied )
2. Required minimum 100us for the stable power before RESET pin transition to HIGH
- Upon power-up the address/command active termination value will automatically be set based off the state of RESET and CKE.
- On the rising edge of RESET the CKE pin is latched to determine the address and command bus termination value.
If CKE is sampled at a zero the address termination is set to 1/2 of ZQ.
If CKE is sampled at a one the address termination is set to ZQ.
- RESET must be maintained at a logic LOW level and CS at a logic high value during power-up to ensure that the DQ outputs will
be in a High-Z state, all active terminators off, and all DLLs off.
3. Minimum 200us delay required prior to applying any executable command after stable power and clock.
4. Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, then RESET and CKE should be
brought to HIGH,
5. Issue a PRECHARGE ALL command following after NOP command.
6. Issue a EMRS command (BA1BA0="01") to enable the DLL.
7. Issue MRS command (BA0BA1 = "00") to reset the DLL and to program the operating parameters.
20K clock cycles are required between the DLL to lock.
8. Issue a PRECHARGE ALL command
9 . Issue at least two AUTO refresh command to update the driver impedance and calibrate the output drivers.
Following these requirements, the GDDR3 SDRAM is ready for normal operation.
V
DDQ
V
DD
V
REF
T0
T1
Ta0
Tb0
Tc0
Td0
Te0
Tf0
CK
CK
RES
tCL
tCH
tATS
tATH
tIS
tIS
tIH
CKE
CKE
tIH
COMMAND
DM
NOP
PRE
LMR
LMR
PRE
AR
AR
ACT
RA
tIS
tIH
CODE
CODE
CODE
tIS
tIH
ALL BANKS
ALL BANKS
A0-A7, A9-A11
A8
CODE
RA
BA
tIS
tIH
tIS
tIH
tIS
tIH
BAO=H,
BA1 =L
BAO=L,
BA1 =L
BA0, BA1
High
High
High
RDQS
WDQS
DQ
T = 200us
T=10ns
tRP
tMRD
tMRD
tRP
20K
tRFC
tRFC
Power-up:
CK stable
Precharge
All Banks
Load Extended
Mode Register
V
and
DD
Load Mode
Register
Precharge
All Banks
1st
2nd
Auto Refresh
Auto Refresh
DLL Reset
8 of 53
Rev. 1.1 November 2005
SAMSUNG [ SAMSUNG ]
