256M GDDR3 SDRAM
K4J55323QG
7.3 MODE REGISTER SET(MRS)
The mode register stores the data for controlling the various operating modes of GDDR3 SDRAM. It programs CAS latency, address-
ing mode, test mode and various vendor specific options to make GDDR3 SDRAM useful for variety of different applications. The
default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for the proper opera-
tion. The mode register is written by asserting low on CS, RAS, CAS and WE (The GDDR3 SDRAM should be in active mode with CKE
already high prior to writing into the mode register). The state of address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS,
CAS and WE going low is written in the mode register. Minimum clock cycles specified as tMRD are required to complete the write oper-
ation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during
operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The Burst
length uses A0 ~ A1. CAS latency (read latency from column address) uses A2, A6 ~ A4. A7 is used for test mode. A8 is used for DLL
reset. A9 ~ A11 are used for Write latency. Refer to the table for specific codes for various addressing modes and CAS latencies.
BA1
0
BA0
0
A11
A10
WL
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DLL
TM
CAS Latency
BT
CL
Burst Length
Test Mode
BA1 BA0
An ~ A0
MRS
EMRS
A7
0
1
mode
Normal
Test
Burst Type
0
0
0
1
A3
0
Burst Type
Sequential
Reserved
DLL
1
A8 DLL Reset
0
1
No
Yes
Write Latency
A11
0
A10
0
A9
0
Write Latency
Reserved
Note : DLL reset is self-clearing
Burst Length
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
1
2
3
4
5
6
7
CAS Latency
A1
0
A0
0
Burst Length
Reserved
Reserved
A2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A6 A5 A4 CAS Latency
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
8
9
10
11
4
5
6
7
0
1
1
0
4
8
1
1
RFU(Reserved for future use) should
stay "0" during MRS cycle
Reserved(12)
Reserved(13)
Reserved(14)
Reserved(15)
Reserved
Reserved
Reserved
Reserved
9 of 53
Rev. 1.1 November 2005
SAMSUNG [ SAMSUNG ]
