64M DDR SDRAM
K4D64163HF
AC OPERATING TEST CONDITIONS (VDD=3.3V±5%, TA= 0 to 65°C)
Parameter
Value
Unit
V
Note
Input reference voltage for CK(for single ended)
CK and CK signal maximum peak swing
CK signal minimum slew rate
0.50*VDDQ
1.5
V
1.0
VREF+0.35/VREF-0.35
VREF
V/ns
V
Input Levels(VIH/VIL)
Input timing measurement reference level
Output timing measurement reference level
Output load condition
V
Vtt
V
See Fig.1
Vtt=0.5*VDDQ
RT=50Ω
Output
Z0=50Ω
VREF
=0.5*VDDQ
CLOAD=30pF
(Fig. 1) Output Load Circuit
CAPACITANCE (VDD=3.3V, TA= 25°C, f=1MHz)
Parameter
Input capacitance( CK, CK )
Symbol
CIN1
Min
1.0
Max
5.0
Unit
pF
pF
Input capacitance(A0~A11, BA0~BA1)
CIN2
1.0
4.0
Input capacitance
( CKE, CS, RAS,CAS, WE )
CIN3
1.0
4.0
pF
Data & DQS input/output capacitance(DQ0~DQ31)
Input capacitance(DM0 ~ DM3)
COUT
CIN4
1.0
1.0
6.5
6.5
pF
pF
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Parameter
Symbol
CDC1
Value
Unit
Decoupling Capacitance between VDD and VSS
Decoupling Capacitance between VDDQ and VSSQ
0.1 + 0.01
0.1 + 0.01
uF
uF
CDC2
Note :
1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
- 12 -
Rev. 1.1(Aug. 2002)
SAMSUNG [ SAMSUNG ]
