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K4D623238B-GC/L45 参数 Datasheet PDF下载

K4D623238B-GC/L45图片预览
型号: K4D623238B-GC/L45
PDF下载: 下载PDF文件 查看货源
内容描述: 64Mbit的DDR SDRAM [64Mbit DDR SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 17 页 / 149 K
品牌: SAMSUNG [ SAMSUNG ]
 浏览型号K4D623238B-GC/L45的Datasheet PDF文件第1页浏览型号K4D623238B-GC/L45的Datasheet PDF文件第2页浏览型号K4D623238B-GC/L45的Datasheet PDF文件第4页浏览型号K4D623238B-GC/L45的Datasheet PDF文件第5页浏览型号K4D623238B-GC/L45的Datasheet PDF文件第6页浏览型号K4D623238B-GC/L45的Datasheet PDF文件第7页浏览型号K4D623238B-GC/L45的Datasheet PDF文件第8页浏览型号K4D623238B-GC/L45的Datasheet PDF文件第9页  
64M DDR SDRAM  
K4D623238B-GC  
512K x 32Bit x 4 Banks Double Data Rate Synchronous RAM  
with Bi-directional Data Strobe and DLL  
FEATURES  
• 2.5V + 5% power supply for device operation  
• 4 DQS’ s ( 1DQS / Byte )  
• VDD/VDDQ = 2.8V ± 5% for -33  
• Data I/O transactions on both edges of Data strobe  
• DLL aligns DQ and DQS transitions with Clock transition  
• Edge aligned data & data strobe output  
• Center aligned data & data strobe input  
• DM for write masking only  
• VDD/VDDQ = 2.5V ± 5% for -60/-55/-50/-45/-40  
• SSTL_2 compatible inputs/outputs  
• 4 banks operation  
• MRS cycle with address key programs  
-. Read latency 3,4,5 (clock)  
• Auto & Self refresh  
-. Burst length (2, 4, 8 and Full page)  
-. Burst type (sequential & interleave)  
• Full page burst length for sequential burst type only  
• Start address of the full page burst should be even  
• All inputs except data & DM are sampled at the positive  
going edge of the system clock  
• 16ms refresh period (2K cycle)  
• 144-Ball FBGA  
• Maximum clock frequency up to 300MHz  
• Maximum data rate up to 600Mbps/pin  
• Differential clock input  
• No Wrtie-Interrupted by Read Function  
ORDERING INFORMATION  
Part NO.  
Max Freq.  
300MHz  
250MHz  
222MHz  
200MHz  
183MHz  
166MHz  
Max Data Rate  
600Mbps/pin  
500Mbps/pin  
444Mbps/pin  
400Mbps/pin  
366Mbps/pin  
333Mbps/pin  
Interface  
Package  
K4D623238B-GC/L33  
K4D623238B-GC/L40  
K4D623238B-GC/L45  
K4D623238B-GC/L50  
K4D623238B-GC/L55  
K4D623238B-GC/L60  
SSTL_2  
144-Ball FBGA  
GENERAL DESCRIPTION  
FOR 512K x 32Bit x 4 Bank DDR SDRAM  
The K4D623238 is 67,108,864 bits of hyper synchronous data rate Dynamic RAM organized as 2 x1,048,976 words by 32  
bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous features with Data Strobe allow  
extremely high performance up to 2.4GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of  
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety  
of high performance memory system applications.  
- 3 -  
Rev. 1.4 (Sep. 2002)  
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