64M DDR SDRAM
K4D623238B-GC
Note 1 :
- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data
strobe and all data associated with that data strobe are coincidentally valid.
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case
output vaild window even then the clock duty cycle applied to the device is better than 45/55%
- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle
variation and replaces tDV
- tQHmin = tHP-X where
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
tQH Timing (CL4, BL2)
tHP
3
0
1
2
4
5
CK, CK
CS
DQS
tDQSQ(max)
tQH
tDQSQ(max)
Qa0
DQ
Qa1
COMMAND
READA
- 14 -
Rev. 1.4 (Sep. 2002)
SAMSUNG [ SAMSUNG ]
