BM28723AMUV
18.3 BCLK High or Low Speed Detection function - continued
Low speed detection clear register (Write Only)
Select Address
0x0B[0]
Explanation of Operation
If 0x1 is written, a low speed detection flag will be cleared.
Caution: When using Auto recovery from clock error function (P.62) , the above-mentioned flag is cleared automatically.
A constraint of the count of judging with high speed flag detection
Default=0x2
Select Address
Explanation of Operation
Set over 0x1. (0x1 to 0x7 are set up) it become 0x0A[1]=0x1 if the BCLK high
speed condition more than the count of setting up is detected continuously.
0x0A[6:4]
A constraint of the count of judging with low speed flag detection
Default=0x2
Select Address
Explanation of Operation
0x0B[6:4]
Set over 0x1. (0x1 to 0x7 are set up) it become 0x0B[1]=0x1 if the BCLK low
speed condition more than the count of setting up is detected continuously.
High speed detection flag valid or invalid
Default=0x0
Select Address
0x0A[7]
Value
0x0
Explanation of Operation
Valid
0x1
Invalid
Low speed detection flag valid or invalid
Default=0x0
Select Address
0x0B[7]
Value
0x0
Explanation of Operation
Valid
0x1
Invalid
The frequency range of BCLK by which high speed detection or low speed detection is carried out is as follows.
Low Speed Detection
Lowest Frequency
(MHz)
High Speed Detection
Highest Frequency
(MHz)
Setting1
Setting2
48kHz (0x0C[1:0]=0x0)
44.1kHz (0x0C[1:0]=0x1)
32kHz (0x0C[1:0]=0x2)
48kHz (0x0C[1:0]=0x0)
44.1kHz (0x0C[1:0]=0x1)
32kHz (0x0C[1:0]=0x2)
48kHz (0x0C[1:0]=0x0)
44.1kHz (0x0C[1:0]=0x1)
32kHz (0x0C[1:0]=0x2)
1.28
1.21
0.88
0.96
0.91
0.66
0.64
0.60
0.44
7.13
6.55
4.76
5.35
4.92
3.57
3.56
3.28
2.38
64fs BCLK (0x03[5:4]=0x0)
48fs BCLK (0x03[5:4]=0x1)
32fs BCLK (0x03[5:4]=0x2)
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TSZ02201-0C1C0E900720-1-2
31.Aug.2018 Rev.001
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