欢迎访问ic37.com |
会员登录 免费注册
发布采购

BM28723AMUV 参数 Datasheet PDF下载

BM28723AMUV图片预览
型号: BM28723AMUV
PDF下载: 下载PDF文件 查看货源
内容描述: [BM1050AF是组合了应对高次谐波的功率因数校正(Power Factor Correction)转换器(以下简称PFC部)与DC/DC转换器(以下简称DC/DC部)的复合LSI。DC/DC部采用准谐振方式动作,有助于实现低EMI。BM1050AF内置650V耐压启动电路。PFC部、DC/DC部均外接开关MOSFET及电流检测电阻,可实现自由度高的电源设计。PFC部采用峰值电流控制。利用带AC电压过低补偿电路的乘法器、应对负载变动的电路、最大功率补偿电路等各种保护电路,提供合适的应用方案。此外,内置跳频功能,有助于实现低EMI。DC/DC部的准谐振方式为软开关动作,有助于实现低EMI。内置脉冲串模式,可降低轻负载时的功耗。内置了软启动功能、脉冲串功能、逐周期过电流限制、过电压保护、过负荷保护等各种保护功能。与微控制器间设有通信控制用端子、外部停止端子,可提供适用于各种应用的系统方案。]
分类和应用: 通信开关控制器微控制器软启动脉冲功率因数校正转换器
文件页数/大小: 82 页 / 5460 K
品牌: ROHM [ ROHM ]
 浏览型号BM28723AMUV的Datasheet PDF文件第56页浏览型号BM28723AMUV的Datasheet PDF文件第57页浏览型号BM28723AMUV的Datasheet PDF文件第58页浏览型号BM28723AMUV的Datasheet PDF文件第59页浏览型号BM28723AMUV的Datasheet PDF文件第61页浏览型号BM28723AMUV的Datasheet PDF文件第62页浏览型号BM28723AMUV的Datasheet PDF文件第63页浏览型号BM28723AMUV的Datasheet PDF文件第64页  
BM28723AMUV  
Description of Function - continued  
18.3 BCLK High or Low Speed Detection function  
BCLK high or low speed detection function counts the period of BCLK rising edge by using internal clock (12MHz to 25MHz) ,  
and if the count value go beyond a constant value, it judge that abnormal speed of clock is occurred such as BCLK speed  
become high or low.  
When using a BCLK speed detection, speed failure detection can be more correctly performed by making a command set  
reflect about an input sampling rate.  
When you validate sampling rate setting, be sure to set up the sampling rate inputted with 0x0C [1:0] command. A high  
speed and the low speed detection flag can set up validity and the invalidity respectively. If valid flag is detected, output is  
muted (immediate mute).  
Valid or invalid frequency value setting up by 0x0C[1:0] command.  
Default=0x0  
Select Address  
0x0A[3]  
Value  
Explanation of Operation  
0x0  
Valid  
0x1  
Invalid  
Setting of input sampling rate  
Default=0x0  
Select Address  
0x0C[1:0]  
Value  
0x0  
Explanation of Operation  
48kHz  
44.1kHz  
32kHz  
0x1  
0x2  
The setting of constraints of a high speed or a low speed detection condition  
Default=0x0  
Select Address  
Value  
Explanation of Operation  
0x0A[2]  
0x0  
±10%  
It can check detection result by reading back.  
The result judged that is once unusual is not cleared until it transmits a clear command, even if the condition of a clock  
returns to normal. It is possible to set the number of judging count of high speed flag detection and low speed flag detection  
by the command. If the error more than the predetermined number is detected, the flag (0x0A[1], 0x0B[1]) becomes 0x1.  
BCLK high speed flag (Read Only)  
Select Address  
0x0A[1]  
Value  
0x0  
Explanation of Operation  
Normal  
High speed detection flag  
0x1  
BCLK low speed flag (Read Only)  
Select Address  
Value  
0x0  
Explanation of Operation  
0x0B[1]  
Normal  
Low speed detection flag  
0x1  
High speed detection clears register (Write Only)  
Select Address  
0x0A[0]  
Explanation of Operation  
If 0x1 writes in, a high speed detection flag will be cleared.  
Caution: When using Auto recovery from clock error function (P.62) , the above-mentioned flag is cleared automatically.  
www.rohm.com  
TSZ02201-0C1C0E900720-1-2  
31.Aug.2018 Rev.001  
© 2018 ROHM Co., Ltd. All rights reserved.  
60/79  
TSZ22111 15 001  
 复制成功!