BM28723AMUV
Description of Function - continued
18 Clock Stop Detection and detection of high speed and low speed or detection of out of sync
18.1 Clock Stop Detection
BM28723AMUV generates internal clock using for audio data processing from inputted several clocks.
By stopping these clock sources, the clocks that is used for audio data processing also stop (Or if that clock does not reach
the frequency speed needed).
Therefore, the detection circuit is needed to avoid that situation.
State of BCLK and LRCLK are detected by using internal clock.
If valid flag is detected, output is muted (Immediate mute).
Internal
frequency
generator
Judge
OK/NG
Clock stop
detecion
circuit
BCLK
Register Read
& Output Stop
LRCLK
Figure 67
Each clock stop is detected when inputted clock stop during the time that is set by command. Detection result can be read
back by command.
In addition, once stop flag is detected, these flags cannot be cleared until clear command is send even though the clock
speed becomes normal.
LRCLK stop detection time
Default=0x2
Select Address
LRCLK 0x07[2:0]
Value
0x0
Explanation of Operation
10μs to 20μs
0x1
0x2
0x3
0x4
0x5
0x6
0x7
20μs to 40μs
50μs to 100μs
100μs to 200μs
200μs to 400μs
300μs to 600μs
400μs to 800μs
500μs to 1000μs
Caution: Detection time has the above-mentioned variation within the limits
BCLK stop detection time
Default=0x0
Select Address
BCLK 0x08[6:4]
Value
0x0
Explanation of Operation
10μs to 20μs
0x1
0x2
0x3
0x4
0x5
0x6
0x7
20μs to 40μs
50μs to 100μs
100μs to 200μs
200μs to 400μs
300μs to 600μs
400μs to 800μs
500μs to 1000μs
Caution: Detection time has the above-mentioned variation within the limits.
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