BM28723AMUV
18.1 Clock Stop Detection - continued
Stop detection flag read back register (Read Only)
Select Address
0x09[5]
Value
Explanation of Operation
0x0
Normal
0x1
0x0
0x1
Detection of LRCLK stop flag
Normal
0x09[4]
Detection of BCLK stop flag
Stop detection flag clear register (Write Only)
Select Address
0x09[1]
Explanation of Operation
LRCLK stop detection flag is cleared by writing 0x1.
BCLK stop detection flag is cleared by writing 0x1.
0x09[0]
Caution: When using Auto recovery from clock error function (P.62) , the above-mentioned flag is cleared automatically.
LRCLK stop flag valid or invalid selection
Default=0x1
Select Address
0x07[3]
Value
0x0
Explanation of Operation
Explanation of Operation
Valid
0x1
Invalid
BCLK stop flag valid or invalid selection
Default=0x0
Select Address
0x08[7]
Value
0x0
Valid
0x1
Invalid
18.2 Out of sync Detection
As for out of sync detecting function, it detects as out of sync error when it counts between the rising edges of LRCLK with
internal clock (49.152MHz), and it shifts more than the definite value, and whether PLL is normally locked is judged.
Input Sampling Frequency
32kHz, 44.1kHz, 48kHz
1023
Count value (Start of counting from 0)
As for the detection result, reading from the register is possible. As a result of the judgment as out of sync once, it is not
cleared until a clear command is transmitted even if the state of the clock returns normally. Moreover, out of sync count
setting is also possible, and if the error is detected more than the number of times set by the command, the flag (0x06[1])
becomes 0x1.
Out of sync flag reading register (Read Only)
Select Address
0x06[1]
Value
Explanation of Operation
0x0
Normal
Synchronous blank detects
0x1
Out of sync flag clear register (Write Only)
Select Address
0x06[0]
Explanation of Operation
When 0x1 is written, the out of sync flag is cleared.
Caution: When using Auto recovery from clock error function (P.62), the above-mentioned flag is cleared automatically.
Out of sync count setting
Default=0x2
Select Address
0x06[6:4]
Explanation of Operation
Set more than 0x1 (Set 0x1 to 0x7).
When the actual detection count of out of sync exceeds the setting,
Select Address 0x07[1] becomes 0x1.
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