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ADSP-BF532SBBZ400 参数 Datasheet PDF下载

ADSP-BF532SBBZ400图片预览
型号: ADSP-BF532SBBZ400
PDF下载: 下载PDF文件 查看货源
内容描述: [16-BIT, 40 MHz, OTHER DSP, PBGA169, ROHS COMPLIANT, PLASTIC, MO-034AAG-2, BGA-169]
分类和应用: 时钟外围集成电路
文件页数/大小: 65 页 / 5323 K
品牌: ROCHESTER [ Rochester Electronics ]
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ADSP-BF531/ADSP-BF532/ADSP-BF533  
Table 9. Pin Descriptions (Continued)  
Driver  
Type1  
Pin Name  
RFS1  
Type Function  
I/O SPORT1 Receive Frame Sync  
C
DR1PRI  
DR1SEC  
TSCLK1  
TFS1  
I
I
SPORT1 Receive Data Primary  
SPORT1 Receive Data Secondary  
I/O SPORT1 Transmit Serial Clock  
I/O SPORT1 Transmit Frame Sync  
D
C
C
C
DT1PRI  
DT1SEC  
UART Port  
RX  
O
O
SPORT1 Transmit Data Primary  
SPORT1 Transmit Data Secondary  
I
UART Receive  
UART Transmit  
TX  
O
C
Real-Time Clock  
RTXI  
I
RTC Crystal Input (This pin should be pulled low when not used.)  
RTC Crystal Output (Does not three-state in hibernate.)  
RTXO  
O
Clock  
CLKIN  
I
Clock/Crystal Input (This pin needs to be at a level or clocking.)  
Crystal Output  
XTAL  
O
Mode Controls  
RESET  
I
I
I
Reset (This pin is always active during core power-on.)  
NMI  
Nonmaskable Interrupt (This pin should be pulled low when not used.)  
Boot Mode Strap (These pins must be pulled to the state required for the desired boot mode.)  
BMODE1–0  
Voltage Regulator  
VROUT1–0  
O
External FET Drive (These pins should be left unconnected when unused and are driven high  
during hibernate.)  
Supplies  
VDDEXT  
VDDINT  
P
P
P
I/O Power Supply  
Core Power Supply  
VDDRTC  
Real-Time Clock Power Supply (This pin should be connected to VDDEXT when not used and should  
remain powered at all times.)  
GND  
G
External Ground  
1 Refer to Figure 32 on Page 44 to Figure 43 on Page 45.  
Rev. H  
| Page 20 of 64 | January 2011  
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