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ADSP-BF532SBBZ400 参数 Datasheet PDF下载

ADSP-BF532SBBZ400图片预览
型号: ADSP-BF532SBBZ400
PDF下载: 下载PDF文件 查看货源
内容描述: [16-BIT, 40 MHz, OTHER DSP, PBGA169, ROHS COMPLIANT, PLASTIC, MO-034AAG-2, BGA-169]
分类和应用: 时钟外围集成电路
文件页数/大小: 65 页 / 5323 K
品牌: ROCHESTER [ Rochester Electronics ]
 浏览型号ADSP-BF532SBBZ400的Datasheet PDF文件第20页浏览型号ADSP-BF532SBBZ400的Datasheet PDF文件第21页浏览型号ADSP-BF532SBBZ400的Datasheet PDF文件第22页浏览型号ADSP-BF532SBBZ400的Datasheet PDF文件第23页浏览型号ADSP-BF532SBBZ400的Datasheet PDF文件第25页浏览型号ADSP-BF532SBBZ400的Datasheet PDF文件第26页浏览型号ADSP-BF532SBBZ400的Datasheet PDF文件第27页浏览型号ADSP-BF532SBBZ400的Datasheet PDF文件第28页  
ADSP-BF531/ADSP-BF532/ADSP-BF533  
ELECTRICAL CHARACTERISTICS  
400 MHz1  
Typical  
500 MHz/533 MHz/600 MHz2  
Parameter  
Test Conditions  
Min  
Max  
Min  
Typical  
Max  
Unit  
VOH  
High Level  
VDDEXT = 1.75 V, IOH = –0.5 mA 1.5  
1.5  
1.9  
2.4  
V
V
V
Output Voltage3  
V
V
DDEXT = 2.25 V, IOH = –0.5 mA 1.9  
2.4  
DDEXT = 3.0 V, IOH = –0.5 mA  
VOL  
Low Level  
VDDEXT = 1.75 V, IOL = 2.0 mA  
0.2  
0.4  
0.2  
0.4  
V
V
Output Voltage3 VDDEXT = 2.25 V/3.0 V,  
IOL = 2.0 mA  
IIH  
High Level Input VDDEXT = Max, VIN = VDD Max  
Current4  
10.0  
50.0  
10.0  
10.0  
10.0  
50.0  
10.0  
10.0  
μA  
μA  
μA  
μA  
IIHP  
High Level Input VDDEXT = Max, VIN = VDD Max  
Current JTAG5  
6
IIL  
Low Level Input VDDEXT = Max, VIN = 0 V  
Current4  
IOZH  
Three-State  
Leakage  
VDDEXT = Max, VIN = VDD Max  
Current7  
6
IOZL  
Three-State  
Leakage  
VDDEXT = Max, VIN = 0 V  
10.0  
89  
10.0  
89  
μA  
Current7  
CIN  
Input  
fIN = 1 MHz, TAMBIENT = 25°C,  
VIN = 2.5 V  
4
4
pF  
Capacitance8  
10  
IDDDEEPSLEEP VDDINT Current in VDDINT = 1.0 V, fCCLK = 0 MHz,  
7.5  
32.5  
mA  
Deep Sleep  
Mode  
TJ = 25°C, ASF = 0.00  
IDDSLEEP  
VDDINT Current in VDDINT = 0.8 V, TJ = 25°C,  
10  
37.5  
mA  
mA  
mA  
mA  
mA  
A  
Sleep Mode  
SCLK = 25 MHz  
11  
IDD-TYP  
IDD-TYP  
IDD-TYP  
IDD-TYP  
VDDINT Current  
VDDINT = 1.14 V, fCCLK = 400 MHz,  
TJ = 25°C  
125  
152  
190  
200  
245  
50  
11  
11  
11  
VDDINT Current  
VDDINT Current  
VDDINT Current  
VDDINT = 1.2 V, fCCLK = 500 MHz,  
TJ = 25°C  
VDDINT = 1.2 V, fCCLK = 533 MHz,  
TJ = 25°C  
VDDINT = 1.3 V, fCCLK = 600 MHz,  
TJ = 25°C  
10  
IDDHIBERNATE VDDEXT Current in VDDEXT = 3.6 V, CLKIN=0 MHz,  
Hibernate State TJ = Max, voltage regulator off  
(VDDINT = 0 V)  
50  
100  
100  
IDDRTC  
VDDRTC Current  
VDDRTC = 3.3 V, TJ = 25°C  
20  
6
20  
16  
A  
10  
IDDDEEPSLEEP VDDINT Current in fCCLK = 0 MHz  
Table 15  
Table 14  
mA  
Deep Sleep  
Mode  
IDD-INT  
VDDINT Current  
fCCLK > 0 MHz  
IDDDEEPSLEEP  
+(Table 17  
ASF)  
IDDDEEPSLEEP mA  
+(Table 17  
ASF)  
1 Applies to all 400 MHz speed grade models. See Ordering Guide on Page 64.  
2 Applies to all 500 MHz, 533 MHz, and 600 MHz speed grade models. See Ordering Guide on Page 64.  
3 Applies to output and bidirectional pins.  
4 Applies to input pins except JTAG inputs.  
Rev. H  
| Page 23 of 64 | January 2011  
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