ADSP-BF531/ADSP-BF532/ADSP-BF533
Table 9. Pin Descriptions (Continued)
Driver
Type1
Pin Name
Type Function
Port F: GPIO/Parallel Peripheral
Interface Port/SPI/Timers
PF0/SPISS
PF1/SPISEL1/TACLK
PF2/SPISEL2
PF3/SPISEL3/PPI_FS3
PF4/SPISEL4/PPI15
PF5/SPISEL5/PPI14
PF6/SPISEL6/PPI13
PF7/SPISEL7/PPI12
PF8/PPI11
PF9/PPI10
PF10/PPI9
PF11/PPI8
PF12/PPI7
PF13/PPI6
PF14/PPI5
PF15/PPI4
JTAG Port
I/O GPIO/SPI Slave Select Input
C
I/O GPIO/SPI Slave Select Enable 1/Timer Alternate Clock Input
I/O GPIO/SPI Slave Select Enable 2
I/O GPIO/SPI Slave Select Enable 3/PPI Frame Sync 3
I/O GPIO/SPI Slave Select Enable 4/PPI 15
I/O GPIO/SPI Slave Select Enable 5/PPI 14
I/O GPIO/SPI Slave Select Enable 6/PPI 13
I/O GPIO/SPI Slave Select Enable 7/PPI 12
I/O GPIO/PPI 11
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
I/O GPIO/PPI 10
I/O GPIO/PPI 9
I/O GPIO/PPI 8
I/O GPIO/PPI 7
I/O GPIO/PPI 6
I/O GPIO/PPI 5
I/O GPIO/PPI 4
TCK
I
JTAG Clock
TDO
O
I
JTAG Serial Data Out
C
TDI
JTAG Serial Data In
TMS
I
JTAG Mode Select
TRST
I
JTAG Reset (This pin should be pulled low if JTAG is not used.)
Emulation Output
EMU
O
C
SPI Port
MOSI
I/O Master Out Slave In
C
C
MISO
I/O Master In Slave Out (This pin should be pulled high through a 4.7 k resistor if booting via the
SPI port.)
SCK
I/O SPI Clock
D
Serial Ports
RSCLK0
RFS0
I/O SPORT0 Receive Serial Clock
I/O SPORT0 Receive Frame Sync
D
C
DR0PRI
DR0SEC
TSCLK0
TFS0
I
I
SPORT0 Receive Data Primary
SPORT0 Receive Data Secondary
I/O SPORT0 Transmit Serial Clock
I/O SPORT0 Transmit Frame Sync
D
C
C
C
D
DT0PRI
DT0SEC
RSCLK1
O
O
SPORT0 Transmit Data Primary
SPORT0 Transmit Data Secondary
I/O SPORT1 Receive Serial Clock
Rev. H
| Page 19 of 64 | January 2011
ROCHESTER [ Rochester Electronics ]
