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ADSP-BF532SBBZ400 参数 Datasheet PDF下载

ADSP-BF532SBBZ400图片预览
型号: ADSP-BF532SBBZ400
PDF下载: 下载PDF文件 查看货源
内容描述: [16-BIT, 40 MHz, OTHER DSP, PBGA169, ROHS COMPLIANT, PLASTIC, MO-034AAG-2, BGA-169]
分类和应用: 时钟外围集成电路
文件页数/大小: 65 页 / 5323 K
品牌: ROCHESTER [ Rochester Electronics ]
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ADSP-BF531/ADSP-BF532/ADSP-BF533  
PIN DESCRIPTIONS  
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors pin  
definitions are listed in Table 9.  
All pins are three-stated during and immediately after reset,  
except the memory interface, asynchronous memory control,  
and synchronous memory control pins. These pins are all  
driven high, with the exception of CLKOUT, which toggles at  
the system clock rate. During hibernate, all outputs are three-  
stated unless otherwise noted in Table 9.  
If BR is active (whether or not RESET is asserted), the memory  
pins are also three-stated. All unused I/O pins have their input  
buffers disabled with the exception of the pins that need pull-  
ups or pull-downs as noted in the table.  
In order to maintain maximum functionality and reduce pack-  
age size and pin count, some pins have dual, multiplexed  
functionality. In cases where pin functionality is reconfigurable,  
the default state is shown in plain text, while alternate function-  
ality is shown in italics.  
Table 9. Pin Descriptions  
Driver  
Pin Name  
Type Function  
Type1  
Memory Interface  
ADDR19–1  
O
Address Bus for Async/Sync Access  
A
A
A
DATA15–0  
I/O Data Bus for Async/Sync Access  
ABE1–0/SDQM1–0  
O
I
Byte Enables/Data Masks for Async/Sync Access  
Bus Request (This pin should be pulled high if not used.)  
Bus Grant  
BR  
BG  
O
O
A
A
BGH  
Bus Grant Hang  
Asynchronous Memory Control  
AMS3–0  
O
I
Bank Select (Require pull-ups if hibernate is used.)  
A
ARDY  
Hardware Ready Control (This pin should be pulled high if not used.)  
AOE  
O
O
O
Output Enable  
Read Enable  
Write Enable  
A
A
A
ARE  
AWE  
Synchronous Memory Control  
SRAS  
O
O
O
O
O
O
O
Row Address Strobe  
A
A
A
A
B
SCAS  
Column Address Strobe  
SWE  
Write Enable  
SCKE  
Clock Enable (Requires pull-down if hibernate is used.)  
CLKOUT  
SA10  
Clock Output  
A10 Pin  
A
A
SMS  
Bank Select  
Timers  
TMR0  
I/O Timer 0  
C
C
C
TMR1/PPI_FS1  
TMR2/PPI_FS2  
PPI Port  
PPI3–0  
I/O Timer 1/PPI Frame Sync1  
I/O Timer 2/PPI Frame Sync2  
I/O PPI3–0  
C
PPI_CLK/TMRCLK  
I
PPI Clock/External Timer Reference  
Rev. H  
| Page 18 of 64 | January 2011