R×5C348A/B
Relation Between the Mode Waveform and the CTFG Bit
• Pulse mode
CTFG bit
INTR pin
Approx. 92µs
Rewriting of the second counter
(Increment of second counter)
)
In the pulse mode, the increment of the second counter is delayed by approximately 92µs from the falling edge of clock pulses. Consequently, time
readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second.
Rewriting the second counter will reset the other time counters of less than 1 second, driving the INTR pin low.
*
• Level mode
CTFG bit
INTR pin
Setting CTFG bit to 0
Setting CTFG bit to 0
(Increment of
second counter)
(Increment of
second counter)
(Increment of
second counter)
13
RICOH [ RICOH ELECTRONICS DEVICES DIVISION ]
