R×5C348A/B
2.1-3 CLEN2 (R×5C348A)
32kHz Clock Output Bit 2
CLEN2 (R
×
5C348A)
Description
(Default setting)
0
1
Enabling the 32-kHz clock circuit
Disabling the 32-kHz clock circuit
For the R×5C348A, setting the CLEN2 bit or the CLEN1 bit (D3 in the control register 2) to 0 specifies generating
clock pulses with the oscillation frequency of the 32.768-kHz crystal oscillator for output from the 32KOUT pin.
Conversely, setting both the CLEN1 and the CLEN2 bit to 1 specifies disabling (“H”) such output.
SCRATCH3 (R×5C348B)
Scratch Bit 3
SCRATCH3 (R
×
5C348B)
Description
(Default setting)
0
1
For the R×5C348B, this bit is intended for scratching and accepts the reading and writing of 0 and 1. The
SCRATCH3 bit will be set to 0 when the XSTP bit is set to 1 in Control Register 2.
2.1-4 TEST
Test Bit
TEST
Settings
0
1
Normal operation mode
Test mode
(Default setting)
The TEST bit is used only for testing in the factory and should normally be set to 0.
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RICOH [ RICOH ELECTRONICS DEVICES DIVISION ]
