R×5C348A/B
FUNCTIONAL DESCRIPTIONS
1. Address Mapping
Data*1
Address
Register
A2
A1
A0
D7
D6
D5
D4
D3
D2
A3
D1
D0
0
1
0
0
0
0
Second Counter
Minute Counter
–*2
S40
S20
S10
S8
S4
S2
S1
0
0
0
0
0
1
1
0
–
–
M40
–
M20
M10
M8
H8
M4
H4
M2
H2
M1
H1
H20
Hour Counter
2
H10
P/A
3
4
5
6
7
8
0
0
0
0
0
1
0
1
1
1
1
0
1
0
0
1
1
0
1
0
1
0
1
0
Day-of-week Counter
Day-of-month Counter
–
–
–
–
–
D20
–
–
–
W4
D4
W2
D2
W1
D1
D10
D8
Month Counter and Century Bit 19/20
–
MO10 MO8 MO4 MO2 MO1
Year Counter
Y80
(0)*4
–
Y40
F6
Y20
F5
Y10
F4
Y8
F3
Y4
F2
Y2
F1
Y1
F0
3
Oscillation Adjustment Register
*
Alarm_W (minute register)
Alarm_W (hour register)
WM40 WM20 WM10 WM8 WM4 WM2 WM1
WH20
9
1
0
0
1
–
–
WH10 WH8 WH4 WH2 WH1
WP/A
A
B
1
1
0
0
1
1
0
1
Alarm_W (Day-of-week register
)
–
–
WW6 WW5 WW4 WW3 WW2 WW1 WW0
DM40 DM20 DM10 DM8 DM4 DM2 DM1
DH20
Alarm_D (minute register)
C
1
1
0
0
Alarm_D (hour register)
–
–
–
DH10 DH8
DH4
DH2
DH1
DP/A
D
E
F
1
1
1
1
1
1
0
1
1
1
0
1
–
–
–
–
–
–
–
Control Register 1*3
Control Register 2*3
WALE DALE 12/24 CLEN2
*
TEST CT2
CT1
CT0
5
5
VDSL VDET SCRATCH1 XSTP CLEN1
*
CTFG WAFG DAFG
1) All the data listed above accept both reading and writing.
*
*
*
2) The data marked with “–” is invalid for writing and reset to 0 for reading.
3) When the XSTP bit is set to 1 in control register 2, all the bits are reset to 0 in oscillation adjustment register 1, control register 1 and control register 2
excluding the XSTP bit.
4) Writing to the oscillation adjustment register requires zero filling the (0) bit.
*
*
5) These bit names apply to the R×5C348A. For the R×5C348B the bit names are SCRATCH2 and SCRATCH3, respectively.
9
RICOH [ RICOH ELECTRONICS DEVICES DIVISION ]
