R×5C348A/B
2.2-4 XSTP
Oscillation Halt Sensing Bit
XSTP
Description
0
1
Sensing a normal condition of oscillation
Sensing a halt of oscillation
(Default setting)
The XSTP bit is for sensing a halt in the oscillation of the crystal oscillator. The oscillation halt sensing circuit
operates only when the CE pin is “L”.
· The XSTP bit will be set to 1 once a halt in the oscillation of the crystal oscillator is caused by such events as
power-on from 0 volts and a drop in supply voltage. The XSTP bit will hold the setting of 1 even after the restart of
oscillation. As such, the XSTP bit can be applied to judge the validity of clock and calendar data after power-on or
a drop in supply voltage.
· When the XSTP bit is set to 1, all bits will be reset to 0 in the oscillation adjustment register, control register 1,
and control register 2, stopping the output from the INTR pin and starting the output of 32.768-kHz clock pulses
from the 32KOUT pin.
· The XSTP bit accepts only the writing of 0, which restarts the oscillation halt sensing circuit. Conversely, setting
the XSTP bit to 1 causes no event.
· It is recommendable to frequently check the XSTP bit for setting errors or data garbles, which may seriously
affect the operation of the R×5C348A/B.
2.2-5 CLEN1 (R×5C348A)
32-kHz Clock Output Bit 1
CLEN1
Description
(Default setting)
0
1
Enabling the 32-kHz clock output
Disabling the 32-kHz clock output
For the R×5C348A, setting the CLEN1 bit or the CLEN2 bit (D4 in control register 1) to 0 specifies generating clock
pulses with the oscillation frequency of the 32.768-kHz crystal oscillator for output from the 32KOUT pin.
Conversely, setting both the CLEN1 bit and the CLEN2 bit to 1 specifies disabling (“H”) such output.
SCRATCH2 (R×5C348B)
Scratch Bit 2
SCRATCH2(R
×
5C348B)
Description
(Default setting)
0
1
For the R×5C348B, this bit is a scratch bit. The SCRATCH2 bit will accept the reading and writing of 0 and 1. The
SCRATCH2 bit will set to 0 when the XSTP bit is set to 1.
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RICOH [ RICOH ELECTRONICS DEVICES DIVISION ]
