RT8859M
Considering the inductance tolerance, the resistor RX has
to be tuned on board by examining the transient voltage.
If the output voltage transient has an initial dip below the
minimum load line requirement with a slow recovery, RX
is chosen too small. Vice versa, if the resistance is too
large the output voltage transient has only a small initial
dip and the recovery becomes too fast, causing a ring
back to occur.
between the OFSApin andGNDis necessary. Designers
can design the offset slew rate by properly setting the
filter bandwidth.
Operation Mode Transition
The RT8859M supports operation mode transition function
at AXGVR for the SetPS command of Intel VR12/IMVP7
CPU. The default operation mode of theAXGVR is PS0,
which is CCM operation. Other operation mode includes
PS2 (single phaseDEM operation).
Using current sense resistor in series with the inductor
can have better accuracy, but at the expense of efficiency.
Considering the equivalent inductance (LESL) of the
current sense resistor, an RC filter is recommended. The
RC filter calculation method is similar to the above
mentioned inductorDCR sensing method.
After receiving SetPS command, the AXG VR will
immediately change to the new operation state. When
the AXGVR receives SetPS command of PS2 operation
mode, the AXG VR operates as a single phase DCM
controller and diode emulation operation is activated.
Therefore, an external driver which supports tri-state
shutdown is required for compatibility with PS2 operation
state.
No Load Offset (SVID & Platform)
TheAXGVR features no load offset function which provides
the possibility of wide range positive offset of output voltage.
The no load offset function can be implemented through
the SVID interface or OFSA pin. Users can disable pin
offset function by simply connecting OFSA pin to GND.
The RT8859M will latch the OFSA status after POR.
If the AXG VR receives dynamic VID change command
(SetVID), the AXG VR will automatically enter PS0
operation mode. After VOUT, AXG reaches target voltage,
theAXGVR will stay at PS0 state and ignore former SetPS
command. Only by resending SetPS command after
SetVID command will the AXG VR be forced into PS2
operation state again.
If pin offset function is enabled, users can decide either to
disable SVID OFS or not by selecting proper resistor
values of TMPMAX pin. After receiving a valid VID, the
RT8859M sinks in 16μA from TMPMAX pin. The voltage
on TMPMAX is
Dynamic VID Enhancement
During a dynamic VID event, the charging (dynamic VID
up) or discharging (dynamic VID down) current causes
unwanted load-line effect which degrades the settling time
performance. TheDVIDApin can be used to compensate
the load-line effect, so that the output voltage can settle
to the target value more quickly.
R2
R1 + R2
(54)
VTMPMAX
=
x VCC − 16μA (R1 // R2)
If VTMPMAX <1V, then the output voltage is
VOUT = VDAC − ILOAD x RDROOP + VPIN−OFS
If VTMPMAX >1V, then the output voltage is
(55)
V
= V
− I
x R
+ V
OUT
DAC
LOAD
DROOP PIN−OFS
During a dynamic VID up event, the RT8859M sources
out a current (IDVIDA) toDVIDApin. The voltage onDVIDA
pin is added to DAC during DVID rising to enhance the
dynamic VID performance. Connecting a capacitor in
parallel with a resistor to DVIDA pin is recommended.
(56)
+ V
SVID−OFS
The pin offset voltage is set by supplying a voltage into
OFSA pin. The linear range of offset pin voltage is from
0.9V to 1.83V. The pin offset voltage can be calculated as
below :
IDVIDA is 8μA during a SetVID_Fast event. If it is a
SetVID_Slow event, IDVIDA automatically shrinks to 2μA
(if slow slew rate is 0.25x fast slew rate) or 4μA(if slow
slew rate is 0.5x fast slew rate). This function is null during
a dynamic VID down event.
VPIN−OFSA = VOFSA − 1.2V
(57)
For example, supplying 1.3V at OFSA pin will achieve
100mV offset at the output. Connecting a filter capacitor
Copyright 2012 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
44
DS8859M-05 July 2012
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
