RT8859M
the AXG VR will trigger UVP latch. The UVP latch will
turn off both high side and low side MOSFETs. When
ROC1b
=
(α −1)×ROC2 + α ×REQU, HOT − REQU, COLD
(1− α)
(69)
UVP is triggered by the AXG VR, the CORE VR will also
where
α =
enter soft shut down sequence. A 3μs delay is used in
UVP detection circuit to prevent false trigger. If platform
OFSA function is enabled (OFSA pin not connected to
GND), the UVP function will be disabled.
RSENSE, HOT
DCR25°C ×[1+ 0.00393×(THOT − 25)]
=
RSENSE, COLD DCR25°C ×[1+ 0.00393×(TCOLD − 25)]
(70)
REQU, T°C = ROC1a // RNTC, T°C
(71)
Under Voltage Lock Out (UVLO)
During normal operation, if the voltage at the VCC orDVD
pin drops below POR threshold, the AXG VR will trigger
UVLO. The UVLO protection forces all high side MOSFETs
and low side MOSFETs off by shutting down internal PWM
logic driver. A3μs delay is used in UVLO detection circuit
to prevent false trigger.
Over Voltage Protection (OVP)
The over voltage protection circuit of theAXGVR monitors
the output voltage via the ISENAN pin after POR. The
supported maximum operating VID of the VR (V(MAX) ) is
stored in the VOUT_Max register. Once VISENAN
exceeds “V(MAX) + 150mV”, OVP is triggered and latched.
The AXG VR will try to turn on low side MOSFETs and
turn off high side MOSFETs of the AXGVR to protect the
CPU. When OVP is triggered by the AXGVR, the CORE
VR will also enter shut down sequence. A 1μs delay is
used in OVP detection circuit to prevent false trigger.Note
that if OFSA pin is higher than 0.9V before power up,
OVP would trigger when “VMAX + 850mV”.
Inductor Selection
The switching frequency and ripple current determine the
inductor value as follows :
V
IN − VOUT
LMIN
=
× TON
(72)
IRipple(MAX)
where tON is the UGATE turn-on period.
Higher inductance yields in less ripple current and hence
higher efficiency. The downside is a slower transient
response of the power stage to load transients. This might
increase the need for more output capacitors, thus driving
up the cost. Select a low loss inductor having the lowest
possibleDC resistance that fits in the allotted dimensions.
The core must be large enough not to be saturated at the
peak inductor current.
Negative Voltage Protection (NVP)
During OVP latch state, the AXG VR also monitors the
ISENAN pin for negative voltage protection. Since the OVP
latch will continuously turn on all low side MOSFETs of
the AXG VR, the AXG VR may suffer negative output
voltage. As a consequence, when the ISENAN voltage
drops below −0.05V after triggering OVP, theAXGVR will
trigger NVP to turn off all low side MOSFETs of the AXG
VR while the high side MOSFETs still remaining off. After
triggering NVP, if the output voltage rises above 0V, the
OVP latch will restart to turn on all low side MOSFETs.
Therefore, the output voltage may bounce between 0V
and −0.05V due to OVP latch and NVP triggering. The
NVP function will be active only after OVP is triggered. A
1μs delay is used inNVP detection circuit to prevent false
trigger.
Output Capacitor Selection
Output capacitors are used to obtain high bandwidth for
the output voltage beyond the bandwidth of the converter
itself. Usually, the CPU manufacturer recommends a
capacitor configuration. Two different kinds of output
capacitors are typically used : bulk capacitors closely
located next to the inductors, and ceramic output
capacitors in close proximity to the load. Latter ones are
for mid-frequency decoupling with especially small ESR
and ESL values, while the bulk capacitors have to provide
enough stored energy to overcome the low frequency
bandwidth gap between the regulator and the CPU.
Under Voltage Protection (UVP)
TheAXGVR implements under voltage protection of VOUT,
AXG. If VFBA is less than the internal reference by 300mV,
Copyright 2012 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
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48
DS8859M-05 July 2012
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
