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RT8859M 参数 Datasheet PDF下载

RT8859M图片预览
型号: RT8859M
PDF下载: 下载PDF文件 查看货源
内容描述: 多相PWM控制器,用于CPU核心供电 [Multi-Phase PWM Controller for CPU Core Power Supply]
分类和应用: 多相元件控制器
文件页数/大小: 51 页 / 729 K
品牌: RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
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RT8859M  
The RT8859M willNOT take any action even when the VR  
output current or temperature exceeds its maximum  
setting at these ADC pins. The maximum level settings  
at theseADC pins are different from over current protection  
or over temperature protection. In other words, these  
maximum level setting pins are only for platform users to  
define their system operating conditions and these  
messages will only be utilized by the CPU.  
Start-Up Sequence  
The RT8859M utilizes an internal soft-start sequence which  
strictly follows Intel VR12/IMVP7 start-up sequence  
specifications. After POR = high and EN = high, the  
controller considers all the power inputs ready and enters  
start-up sequence. If VINITIAL = 0, VOUT is programmed to  
stay at 0V for 2ms waiting for SVID command. If VINITIAL  
0 , VOUT will ramp up to VINITIAL voltage (which is not  
zero) immediately after both POR = high and EN= high.  
After VOUT reaches target VINITIAL, VOUT will stay at VINITIAL  
waiting for SVID command. After the RT8859M receives  
valid VID code (typically SetVID_Slow command), VOUT  
will ramp up to the target voltage with specified slew rate  
(see section Data and Configuration Register). After  
VOUT reaches target voltage (VIDvoltage for VINITIAL = 0 or  
VINITIAL Setting  
The initial startup voltage of the RT8859M can be set by  
platform users through the SETINI and the SETINIApins.  
Voltage divider circuits are recommended to be applied to  
the SETINI and the SETINIApins. The initial startup voltage  
relates to the SETINI pin voltage setting as shown in Table  
4. Recommended voltage setting at the SETINIA pin is  
also shown in Table 4.  
VINITIAL for VINITIAL 0), the RT8859M will send out  
VR_RDY signal to indicate that the power state of the  
RT8859M is ready. The VR ready circuit is an open-drain  
structure, so a pull-up resistor connected to a voltage  
source is recommended.  
Table 4. SETINI (SETINIA) Pin Setting  
Initial Startup  
Voltage  
Recommended SETINI Pin  
Voltage  
7
8
Power Down Sequence  
1.5V  
1.1V  
1V  
x VCC 4.375V  
x VCC 3.125V  
x VCC 1.875V  
Similar to the start-up sequence, the RT8859M also  
utilizes a soft shutdown mechanism during turn-off. After  
EN= low, the internal reference voltage (positive terminal  
of compensation EA) starts ramping down with 3.125mV/  
μs slew rate, and VOUT will follow the reference voltage to  
0V.After VOUT drops below 0.2V, the RT8859M shuts down  
and all functions (drivers) are disabled. The VR_RDY and  
VRA_RDY will be pulled down immediately after POR =  
low or EN = low.  
5
8
3
8
3
16  
0.9V  
0V  
x VCC 0.9375V  
1
16  
x VCC 0.3125V or GND  
Copyright 2012 Richtek Technology Corporation. All rights reserved.  
©
is a registered trademark of Richtek Technology Corporation.  
DS8859M-05 July 2012  
www.richtek.com  
31  
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