RX62N Group, RX621 Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (33 / 35)
Module
Register
Number Access
Number of
Address
Abbreviation Register Name
Abbreviation of Bits
Size
Access Cycles
000A 0290h
USB1
USB1
USB1
USB1
USB1
USB1
USB1
USB1
USB1
USB1
USB1
USB1
USB1
USB1
USB1
USB1
USB
Pipe 1 transaction counter enable
register
PIPE1TRE
PIPE1TRN
PIPE2TRE
PIPE2TRN
PIPE3TRE
PIPE3TRN
PIPE4TRE
PIPE4TRN
PIPE5TRE
PIPE5TRN
DEVADD0
DEVADD1
DEVADD2
DEVADD3
DEVADD4
DEVADD5
DPUSR0R
DPUSR1R
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
32
32
16
at least 9
PCLK*9
000A 0292h
000A 0294h
000A 0296h
000A 0298h
000A 029Ah
000A 029Ch
000A 029Eh
000A 02A0h
000A 02A2h
000A 02D0h
000A 02D2h
000A 02D4h
000A 02D6h
000A 02D8h
000A 02DAh
000A 0400h
000A 0404h
Pipe 1 transaction counter register
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
32
32
at least 9
PCLK*9
Pipe 2 transaction counter enable
register
at least 9
PCLK*9
Pipe 2 transaction counter register
at least 9
PCLK*9
Pipe 3 transaction counter enable
register
at least 9
PCLK*9
Pipe 3 transaction counter register
at least 9
PCLK*9
Pipe 4 transaction counter enable
register
at least 9
PCLK*9
Pipe 4 transaction counter register
at least 9
PCLK*9
Pipe 5 transaction counter enable
register
at least 9
PCLK*9
Pipe 5 transaction counter register
at least 9
PCLK*9
Device address 0 configuration register
Device address 1 configuration register
Device address 2 configuration register
Device address 3 configuration register
Device address 4 configuration register
Device address 5 configuration register
at least 9
PCLK*9
at least 9
PCLK*9
at least 9
PCLK*9
at least 9
PCLK*9
at least 9
PCLK*9
at least 9
PCLK*9
Deep standby USB transceiver control/
pin monitor register
1 to 2PCLK*8
USB
Deep standby USB suspend/resume
interrupt register
1 to 2PCLK*8
000C 0000h
000C 0008h
000C 0010h
000C 0018h
EDMAC
EDMAC
EDMAC
EDMAC
EDMAC mode register
EDMR
32
32
32
32
32
32
32
32
4 to 5 ICLK
4 to 5 ICLK
4 to 5 ICLK
4 to 5 ICLK
EDMAC transmit request register
EDMAC receive request register
EDTRR
EDRRR
TDLAR
Transmit descriptor list start address
register
000C 0020h
EDMAC
Receive descriptor list start address
register
RDLAR
32
32
4 to 5 ICLK
000C 0028h
000C 0030h
EDMAC
EDMAC
ETHERC/EDMAC status register
EESR
32
32
32
32
4 to 5 ICLK
4 to 5 ICLK
ETHERC/EDMAC status interrupt
permission register
EESIPR
000C 0038h
EDMAC
Transmit/receive status copy enable
register
TRSCER
32
32
4 to 5 ICLK
000C 0040h
000C 0048h
000C 0050h
000C 0058h
EDMAC
EDMAC
EDMAC
EDMAC
Receive missed-frame counter register
Transmit FIFO threshold register
FIFO depth register
RMFCR
TFTR
FDR
32
32
32
32
32
32
32
32
4 to 5 ICLK
4 to 5 ICLK
4 to 5 ICLK
4 to 5 ICLK
Receiving method control register
RMCR
R01DS0052EJ0110 Rev.1.10
Feb 10, 2011
Page 84 of 146
RENESAS [ RENESAS TECHNOLOGY CORP ]
