RX62N Group, RX621 Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (29 / 35)
Module
Register
Number Access
Number of
Address
Abbreviation Register Name
Abbreviation of Bits
Size
Access Cycles
0009 084Fh
0009 0850h
0009 0851h
0009 0852h
0009 0853h
0009 0854h
0009 0856h
0009 0858h
000A 0000h
000A 0004h
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
USB0
USB0
Transmit error count register
TECR
ECSR
CSSR
MSSR
MSMR
TSR
8
8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
3 to 4 PCLK*8
Error code store register
8
8
Channel search support register
Mailbox search status registe
Mailbox search mode registe
Time stamp registerr
8
8
8
8
8
8
16
16
8
8, 16
8, 16
8
Acceptance filter support register
Test control register
AFSR
TCR
System configuration control register
System configuration status register 0
SYSCFG
SYSSTS0
16
16
16
16
at least 9
PCLK*9
000A 0008h
USB0
Device state control register 0
DVSTCTR0
16
16
at least 9
PCLK*9
000A 0014h
000A 0018h
000A 001Ch
000A 0020h
000A 0022h
000A 0028h
000A 002Ah
000A 002Ch
000A 002Eh
000A 0030h
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
CFIFO port register
CFIFO
16
16
16
16
16
16
16
16
16
16
8, 16
8, 16
8, 16
16
3 to 4 PCLK*8
3 to 4 PCLK*8
3 to 4 PCLK*8
3 to 4 PCLK*8
3 to 4 PCLK*8
3 to 4 PCLK*8
3 to 4 PCLK*8
3 to 4 PCLK*8
3 to 4 PCLK*8
D0FIFO port register
D0FIFO
D1FIFO port register
D1FIFO
CFIFO port select register
CFIFO port control register
D0FIFO port select register
D0FIFO port control register
D1FIFO port select register
D1FIFO port control register
Interrupt enable register 0
CFIFOSEL
CFIFOCTR
D0FIFOSEL
D0FIFOCTR
D1FIFOSEL
D1FIFOCTR
INTENB0
16
16
16
16
16
16
at least 9
PCLK*9
000A 0032h
000A 0036h
000A 0038h
000A 003Ah
000A 003Ch
000A 0040h
000A 0042h
000A 0046h
000A 0048h
000A 004Ah
000A 004Ch
000A 004Eh
000A 0050h
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
Interrupt enable register 1
BRDY interrupt enable register
NRDY interrupt enable register
BEMP interrupt enable register
SOF output configuration register
Interrupt status register 0
INTENB1
BRDYENB
NRDYENB
BEMPENB
SOFCFG
INTSTS0
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
at least 9
PCLK*9
at least 9
PCLK*9
at least 9
PCLK*9
at least 9
PCLK*9
at least 9
PCLK*9
at least 9
PCLK*9
Interrupt status register 1
INTSTS1
at least 9
PCLK*9
BRDY interrupt enable register
NRDY interrupt status register
BEMP interrupt status register
Frame number register
BRDYSTS
NRDYSTS
BEMPSTS
FRMNUM
DVCHGR
USBADDR
at least 9
PCLK*9
at least 9
PCLK*9
at least 9
PCLK*9
at least 9
PCLK*9
Device state change register
USB address register
at least 9
PCLK*9
at least 9
PCLK*9
R01DS0052EJ0110 Rev.1.10
Feb 10, 2011
Page 80 of 146
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