RX62N Group, RX621 Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (34 / 35)
Module
Register
Number Access
Number of
Address
Abbreviation Register Name
Abbreviation of Bits
Size
Access Cycles
000C 0064h
000C 0068h
000C 006Ch
EDMAC
EDMAC
EDMAC
Transmit FIFO underrun counter
TFUCR
RFOCR
IOSR
32
32
32
32
4 to 5 ICLK
4 to 5 ICLK
4 to 5 ICLK
Receive FIFO overflow counter
32
Independent output signal setting
register
32
000C 0070h
EDMAC
Flow control start FIFO threshold setting FCFTR
register
32
32
4 to 5 ICLK
000C 0078h
000C 007Ch
000C 00C8h
000C 00CCh
000C 00D4h
000C 00D8h
EDMAC
EDMAC
EDMAC
EDMAC
EDMAC
EDMAC
Receive data padding insert register
Transmit interrupt setting register
Receive buffer write address register
RPADIR
TRIMD
32
32
32
32
32
32
32
32
32
32
32
32
4 to 5 ICLK
4 to 5 ICLK
4 to 5 ICLK
4 to 5 ICLK
4 to 5 ICLK
4 to 5 ICLK
RBWAR
Receive descriptor fetch address register RDFAR
Transmit buffer read address register
TBRAR
TDFAR
Transmit descriptor fetch address
register
000C 0100h
000C 0108h
000C 0110h
000C 0118h
000C 0120h
000C 0128h
000C 0140h
ETHERC
ETHERC
ETHERC
ETHERC
ETHERC
ETHERC
ETHERC
ETHERC mode register
Receive frame length register
ETHERC status register
ETHERC interrupt enable register
PHY interface register
ECMR
RFLR
ECSR
ECSIPR
PIR
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4 to 5 ICLK
4 to 5 ICLK
4 to 5 ICLK
4 to 5 ICLK
4 to 5 ICLK
4 to 5 ICLK
4 to 5 ICLK
PHY status register
PSR
Random number generation counter
upper limit setting register
RDMLR
000C 0150h
000C 0154h
000C 0158h
000C 0160h
000C 0164h
ETHERC
ETHERC
ETHERC
ETHERC
ETHERC
IPG register
IPGR
32
32
32
32
32
32
32
32
32
32
4 to 5 ICLK
4 to 5 ICLK
4 to 5 ICLK
4 to 5 ICLK
4 to 5 ICLK
Automatic PAUSE frame register
Manual PAUSE frame register
PAUSE frame receive counter register
APR
MPR
RFCF
TPAUSER
Automatic PAUSE frame retransmit
count register
000C 0168h
000C 016Ch
ETHERC
ETHERC
PAUSE frame retransmit counter register TPAUSECR
32
32
32
32
4 to 5 ICLK
4 to 5 ICLK
Broadcast frame receive count setting
register
BCFRR
000C 01C0h
000C 01C8h
000C 01D0h
000C 01D4h
000C 01D8h
000C 01DCh
000C 01E4h
000C 01E8h
000C 01ECh
000C 01F0h
000C 01F4h
ETHERC
ETHERC
ETHERC
ETHERC
ETHERC
ETHERC
ETHERC
ETHERC
ETHERC
ETHERC
ETHERC
MAC address high register
MAC address low register
MAHR
MALR
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4 to 5 ICLK
4 to 5 ICLK
4 to 5 ICLK
4 to 5 ICLK
4 to 5 ICLK
4 to 5 ICLK
4 to 5 ICLK
4 to 5 ICLK
4 to 5 ICLK
4 to 5 ICLK
4 to 5 ICLK
Transmit retry over counter register
TROCR
Delayed collision detect counter register CDCR
Lost carrier counter register
LCCR
Carrier not detect counter register
CNDCR
CRC error frame receive counter register CEFCR
Frame receive error counter register FRECR
Too-short frame receive counter register TSFRCR
Too-long frame receive counter register
TLFRCR
RFCR
Residual-bit frame receive counter
register
000C 01F8h
ETHERC
Multicast address frame receive counter MAFCR
register
32
32
4 to 5 ICLK
007F C402h
007F C410h
FLASH
FLASH
Flash mode register
FMODR
FASTAT
8
8
8
8
2 to 3 PCLK*8
2 to 3 PCLK*8
Flash access status register
R01DS0052EJ0110 Rev.1.10
Feb 10, 2011
Page 85 of 146
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