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R5F562N8BDFB 参数 Datasheet PDF下载

R5F562N8BDFB图片预览
型号: R5F562N8BDFB
PDF下载: 下载PDF文件 查看货源
内容描述: 100 MHz的32位MCU的RX与FPU , 165 DMIPS ,高达512 KB的闪存,以太网, USB 2.0 [100 MHz 32-bit RX MCU with FPU, 165 DMIPS, up to 512-Kbyte Flash, Ethernet, USB 2.0]
分类和应用: 闪存以太网
文件页数/大小: 146 页 / 1021 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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RX62N Group, RX621 Group  
1. Overview  
Table 1.9  
Pin Functions (2 / 7)  
Classifications  
Pin Name  
I/O  
Description  
Bus control  
RD#  
Output  
Strobe signal which indicates that reading from the external bus  
interface space is in progress.  
WR#  
Output  
Output  
Strobe signal which indicates that writing to the external bus  
interface space is in progress, in 1-write strobe mode.  
WR0# to WR3#  
Strobe signals which indicate that any group of data bus pins  
(D7 to D0, D15 to D8, D23 to D16, and D31 to D24) is valid in  
writing to the external bus interface space, in byte strobe mode.  
BC0# to BC3#  
Output  
Strobe signals which indicate that any group of data bus pins  
(D7 to D0, D15 to D8, D23 to D16, and D31 to D24) is valid in  
access to the external bus interface space, in 1-write strobe  
mode.  
WE#  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output pin for SDRAM write enable signals.  
Output pin for SDRAM column address strobe signals.  
Output pin for SDRAM row address strobe signals.  
Output pin for SDRAM clock enable signals.  
Output pins for SDRAM I/O data mask enable signals.  
Output pin for SDRAM chip select signals.  
Select signals for areas 0 to 7.  
CAS#  
RAS#  
CKE  
DQM0 to DQM34  
SDCS#  
CS0#-A/CS0#-B  
CS1#-A/CS1#-B/CS1#-C  
CS2#-A/CS2#-B/CS2#-C  
CS3#-A/CS3#-B/CS3#-C  
CS4#-A/CS4#-B/CS4#-C  
CS5#-A/CS5#-B/CS5#-C  
CS6#-A/CS6#-B/CS6#-C  
CS7#-A/CS7#-B/CS7#-C  
WAIT#-A/WAIT#-B/  
WAIT#-C/WAIT#-D  
Input  
Input pins for wait request signals in access to the external  
space.  
EXDMA controller  
EDREQ0-A/EDREQ0-B/  
EDREQ0-C  
Input  
Input pins for external requests of channel 0.  
EDREQ1-A/EDREQ1-B/  
EDREQ1-C  
Input  
Input pins for external requests of channel 1.  
EDACK0-A/EDACK0-B/  
EDACK0-C  
Output  
Output  
Output pins for single address transfer acknowledge signals of  
channel 0.  
EDACK1-A/EDACK1-B/  
EDACK1-C  
Output pins for single address transfer acknowledge signals of  
channel 1.  
Interrupt  
NMI  
Input  
Input  
Non-maskable interrupt request signal.  
Interrupt request signals.  
IRQ0-A/IRQ0-B  
IRQ1-A/IRQ1-B  
IRQ2-A/IRQ2-B  
IRQ3-A/IRQ3-B  
IRQ4-A/IRQ4-B  
IRQ5-A/IRQ5-B  
IRQ6-A/IRQ6-B  
IRQ7-A/IRQ7-B  
IRQ8-A/IRQ8-B  
IRQ9-A/IRQ9-B  
IRQ10-A/IRQ10-B  
IRQ11-A/IRQ11-B  
IRQ12  
IRQ13-A/IRQ13-B  
IRQ14  
IRQ15-A/IRQ15-B  
R01DS0052EJ0110 Rev.1.10  
Feb 10, 2011  
Page 41 of 146  
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