R8C/13 Group
5.4 Voltage Detection Circuit
Voltage detection interrupt register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
D4INT
Address
001F16
After reset(10)
Reset input : 0016
RESET pin = H retaining : 01000001
2
Bit symbol
D40
RW
RW
Bit name
Function
Voltage detection interrupt
enable bit(7)
0 : Disable
1 : Enable
0: Digital filter enable mode (digital
filter circuit enabled)
1: Digital filter disable mode (digital
filter circuit disabled)
Voltage detection digital filter
disable mode select bit
D41
RW
Voltage change detection
flag(3, 4, 5)
0: Not detected
1: Vdet passing detection
RW
RW
D42
D43
DF0
WDT overflow detect flag(3, 4)
Sampling clock select bit
0: Not detected (flag clear)
1: Detected
b5b4
RW
00 : fRING-S divided by 1
01 : fRING-S divided by 2
10 : fRING-S divided by 4
11 : fRING-S divided by 8
DF1
D46
RW
RW
0: Voltage detection interrupt
request is generated when
passing through Vdet
Voltage monitor mode select
bit(6)
1: Hardware reset 2 when
passing through Vdet
D47
Voltage detection condition
select bit(11)
Voltage detection interrupt
request is generated
or hardware reset 2
when Vcc passes Vdet(9)
0: Over Vdet
RW
1: Below Vdet
NOTES:
1. Set the PRC3 bit in the PRCR register to “1” (write enable) before writing to this register.
2. If the voltage detection interrupt needs to be used to get out of stop mode again after once used for that
purpose, reset the D41 bit by writing a “0” and then a “1”.
3. Valid when the VC27 bit in the VCR2 register is set to “1” (voltage detection circuit enabled).
4. If the VC27 bit is set to “0” (voltage detection circuit disabled), the D42 and D43 bits are set to “0” (not detected).
5. This bit is set to “0” by writing a “0” in a program. (writing a “1” has no effect.)
6. Valid when the D40 bit is set to “1” (voltage detection interrupt enabled).
7. The D40 bit is valid when the VC27 bit in the VCR2 register is set to “1” (voltage detection circuit enabled).
When setting the D40 bit to “1”, the following setting is required.
(1) Set the VC27 bit “1”.
(2) Wait for td(E-A) until the detecter circuit operates.
(3) Wait for the sampling time (the sampling clock which is selected in the DF0 bit to DF1 bit times 4 cycles.)
(4) Set the D40 bit to “1”.
(5) Set the CM14 bit in the CM1 register to “0” (low-speed on-chip oscillator on).
8. Valid when the D41 bit is set to “1” (digital filter disabled mode).
9. The D46 bit can be selected.
10. The software reset or the watchdog timer reset do not affect this register.
11. When the D46 bit is set to “1” (hardware reset 2 when Vdet passes), set the D47 bit to “1” (below Vdet).
(Do not set to “0”).
Figure 5.9 D4INT Register
Rev.1.20 Jan 27, 2006 page 23 of 205
REJ09B0111-0120
RENESAS [ RENESAS TECHNOLOGY CORP ]
