R8C/13 Group
VCC
0.1V to 2.7V
0V
RESET
0V
RESET
Vcc
0.8VCC or above
about 5 kΩ
within td(P-R)
3
(3)
det
Vdet
V
V
V
cc min
por2
Vpor1
(1,2)
Sampling time
tw(por2)
tw(Vpor2 –Vdet)
t
w(por1) tw(Vpor1–Vdet)
Internal reset signal
(“L” effective)
1
1
X 32
X 32
f
RING-S
f
RING-S
NOTES:
1. Hold the voltage of the microcomputer operation voltage range (Vccmin or above) within sampling time.
2. A sampling clock is selectable. Refer to “5.4 Voltage Detection Circuit” for details.
3. Vdet shows the voltage detection level of the voltage detection circuit. Refer to “5.4 Voltage Detection Circuit” for details.
4. Refer to Table 16.7, 16.8 for electrical characteristics.
Figure 5.6 Power-on Reset Operation
Rev.1.20 Jan 27, 2006 page 19 of 205
REJ09B0111-0120
RENESAS [ RENESAS TECHNOLOGY CORP ]
