R8C/13 Group
5.4 Voltage Detection Circuit
5.0 V
5.0 V
V
det
1
V
CC
x 32
fRING
Sampling time
(3 to 4 clock)
Internal reset signal
(D46 bit=1)
VC13 bit
Set to“1” by program (voltage
detection circuit enabled)
VC27 bit
Interrupt acknowledged
Interrupt acknowledged
Sampling time
(3 to 4 clock)
Voltage detection
interrupt request
(D46 bit=0)
The above applies to the following conditions.
• D4INT register D40 bit = 1 (voltage detection interrupt enabled)
• D4INT register D41 bit = 0 (digital filter enabled mode)
Sampling time : 4 cycles of sampling clock selected in DF0 bit to DF1 bit
Figure 5.10 Operation Example of Voltage Detection Circuit
Rev.1.20 Jan 27, 2006 page 24 of 205
REJ09B0111-0120