R8C/13 Group
5.4 Voltage Detection Circuit
Voltage detection interrupt generation circuit
DF1 to DF0
Voltage detection circuit
=002
=012
=102
=112
D42 bit is set to “0”(not detected)
by writing a “0” in a program.
When VC27 bit is set to “0”
(voltage detection circuit
VC27
f
RING-S
1/2
1/2
1/2
disabled), D42 bit is set to “0” .
VC13
Watchdog
timer interrupt
signal
V
CC1
+
-
Noise rejection
circuit
Noise
canceller
Digital
filter
Voltage
detection
signal
D42
Internal
reference
voltage
(Canceller width: 200 ns)
Voltage
Voltage detection signal
is “H” when VC27 bit= 0
(disabled)
detection
Non-maskable
interrupt signal
interrupt signal
D41
Oscillation stop
detection
CM10
interrupt signal
Watchdog timer block
D43
D47
D40
D46
Hardware reset 2
Watchdog timer
underflow signal
This bit is set to “0”(not detected) by writing a “0” in a program.
D40, D41, D42, D43, DF0, DF1, D46, D47: Bits in D4INT register
VC13: Bit in VCR1 register
CM02: Bit in CM0 register
CM10: Bit in CM1 register
VC27: Bit in VCR2 register
Figure 5.13 Operation Detection Interrupt Generation Block
VCC
VC13 bit
sampling
sampling
sampling
sampling
No voltage detection interrupt
signals are generated when D42 bit
is “H”.
(
Output of digital filter 2)
D42 bit
Set D42 bit to “0”
in a program (not
detected)
Set D42 bit to “0”
in a program (not
detected)
Voltage detection
interrupt signal
NOTES:
D42: Bit in D4INT register
VC13: Bit in VCR1 register
1. D40 is “1”(voltage detection interrupt enabled).
2. Output of the digital filter shown in Figure 5.11
Figure 5.14 Voltage Detection Interrupt Generation Circuit Operation Example
Rev.1.20 Jan 27, 2006 page 27 of 205
REJ09B0111-0120
RENESAS [ RENESAS TECHNOLOGY CORP ]
