R8C/13 Group
5.2 Software Reset, 5.3 Watchdog Timer Reset
5.2 Software Reset
When the PM03 bit in the PM0 register is set to “1” (microcomputer reset), the microcomputer has its
pins, CPU, and SFR initialized. Then the program is executed starting from the address indicated by
the reset vector.
After reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected for the CPU.
Some SFRs are not initialized by the software reset. Refer to Chapter 4, “SFR.”
5.3 Watchdog Timer Reset
Where the PM12 bit in the PM1 register is “1” (reset when watchdog timer underflows), the microcom-
puter initializes its pins, CPU and SFR if the watchdog timer underflows. Then the program is ex-
ecuted starting from the address indicated by the reset vector.
After reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected for the CPU.
Some SFRs are not initialized by the watchdog timer reset. Refer to Chapter 4, “SFR.”
Rev.1.20 Jan 27, 2006 page 20 of 205
REJ09B0111-0120
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