R8C/13 Group
5.1 Hardware Reset
b15
b0
000016
000016
000016
000016
000016
000016
000016
Data register(R0)
Data register(R1)
Data register(R2)
Data register(R3)
Address register(A0)
Address register(A1)
Frame base register(FB)
b19
b0
b0
0000016
Interrupt table register(INTB)
Program counter(PC)
Content of addresses 0FFFE16 to 0FFFC16
b15
User stack pointer(USP)
000016
000016
000016
Interrupt stack pointer(ISP)
Static base register(SB)
b15
b0
b0
Flag register(FLG)
000016
b15
b8 b7
IPL
U I O B S Z D C
Figure 5.1 CPU Register Status After Reset
f
RING-S
More than 20 cycles are needed(1)
Internal on-chip
oscillation
Flash memory activated time
(CPU clock ✕ 64 cycles)
CPU clock ✕ 28cycles
CPU clock
0FFFE16
0FFFC16
Address
(Internal address signal)
0FFFD16
Content of reset vector
NOTES:
1. This shows hardware reset
Figure 5.2 Reset Sequence
Rev.1.20 Jan 27, 2006 page 15 of 205
REJ09B0111-0120
RENESAS [ RENESAS TECHNOLOGY CORP ]
