3858 Group
Internal synchronous
clock selection bits
1/8
X
CIN
1/16
1/32
Data bus
“10”
Main clock division ratio
selection bits (Note)
1/64
“00”
“01”
1/128
1/256
X
IN
P0
3
latch
Serial I/O2 synchronous
clock selection bit
“0”
“1”
P03/SRDY2
S
RDY2
Synchronous circuit
“1”
S
RDY2 output enable bit
“0”
External clock
Serial I/O2
synchronous clock
selection bit
P02 latch
Optional transfer bits (3)
Serial I/O counter 2 (3)
“0”
P02/SCLK2
Serial I/O2
“1”
interrupt request
Serial I/O2 port selection bit
P01 latch
“0”
P0
1
/SOUT2
/SIN2
“1”
Serial I/O2 port selection bit
Serial I/O2 register (8)
P0
0
P43 latch
“0”
D
P4
3/SCMP2/INT2
Q
“1”
Serial I/O2 I/O comparison
signal control bit
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 6 and 7 of CPU mode register.
Fig. 42 Block diagram of Serial I/O2
Transfer clock (Note 1)
Write-in signal to
serial I/O2 register
(Note 2)
.
Serial I/O2 output
SOUT2
D0
D1
D2
D3
D4
D5
D6
D7
Serial I/O2 input SIN2
Receive enable signal SRDY2
Serial I/O2 interrupt request bit set
Notes
1: When the internal clock is selected as a transfer clock, the f(XIN) clock division (f(XCIN) in low-speed mode) can be selected
by setting bits 0 to 2 of serial I/O2 control register 1.
2: When the internal clock is selected as a transfer clock, the SOUT2 pin has high impedance after transfer completion.
Fig. 43 Timing chart of Serial I/O2
Rev.1.10 Apr 3, 2006 page 48 of 75
REJ03B0139-0110
RENESAS [ RENESAS TECHNOLOGY CORP ]
