3858 Group
“11”
“00”
“01”
X
IN
(1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024)
Divider
Count source
selection bit
“10”
X
CIN
Data bus
Main clock
division ratio
selection bits
Prescaler X latch (8)
Timer X latch (8)
Timer X (8)
f(XCIN
)
Pulse width
Timer mode
Pulse output mode
measurement
mode
To timer X interrupt
request bit
Prescaler X (8)
Timer X count stop bit
CNTR0 active edge
switch bit
Event
counter
mode
P27/CNTR0
“0”
To CNTR0 interrupt
request bit
“1”
CNTR0 active
edge switch bit
“1”
“0”
Q
Q
T
Toggle flip-flop
R
Port P27
latch
Timer X latch write pulse
Pulse output mode
Port P27
direction register
Pulse output mode
Data bus
Count source selection bit
Clock for timer Y
f(XCIN
Timer Y latch (8)
Timer Y (8)
Prescaler Y latch (8)
Pulse width
measurement
mode
)
Timer mode
Pulse output mode
To timer Y interrupt
request bit
Prescaler Y (8)
Timer Y count stop bit
CNTR1 active edge
switch bit
Event
counter
mode
P40/CNTR1
“0”
To CNTR1 interrupt
request bit
“1”
CNTR1 active
edge switch bit
“1”
“0”
Q
Q
T
Toggle flip-flop
R
Port P40
latch
Timer Y latch write pulse
Pulse output mode
Port P40
direction register
Pulse output mode
Data bus
Timer 1 latch (8)
Timer 1 (8)
Timer 2 latch (8)
Timer 2 (8)
Prescaler 12 latch (8)
Prescaler 12 (8)
To timer 2 interrupt
request bit
Clock for timer 12
To timer 1 interrupt
request bit
Fig. 17 Block diagram of timer X, timer Y, timer 1, and timer 2
Rev.1.10 Apr 3, 2006 page 24 of 75
REJ03B0139-0110
RENESAS [ RENESAS TECHNOLOGY CORP ]
