M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
2
8.6.4 I C Control Register
(3) Bit 4: data format selection bit (ALS)
2
The I C control register (address 00DA16) controls the data commu-
This bit decides whether or not to recognize slave addresses. When
this bit is set to “0,” the addressing format is selected, so that ad-
dress data is recognized. When a match is found between a slave
address and address data as a result of comparison or when a gen-
nication format.
(1) Bits 0 to 2: bit counter (BC0–BC2)
2
These bits decide the number of bits for the next 1-byte data to be
transmitted. An interrupt request signal occurs immediately after the
number of bits specified with these bits are transmitted.
eral call (refer to “8.6.5 I C Status Register,” bit 1) is received, trans-
mission processing can be performed. When this bit is set to “1,” the
free data format is selected, so that slave addresses are not recog-
nized.
When a START condition is received, these bits become “0002” and
the address data is always transmitted and received in 8 bits.
(4) Bit 5: addressing format selection bit (10BIT SAD)
This bit selects a slave address specification format. When this bit is
set to “0,” the 7-bit addressing format is selected. In this case, only
2
(2) Bit 3: I C-BUS interface use enable bit (ESO)
2
This bit enables usage of the multimaster I C BUS interface. When
2
this bit is set to “0,” interface is in the disabled status so the SDA and
the SCL become high-impedance. When the bit is set to “1,” use of
the interface is enabled.
the high-order 7 bits (slave address) of the I C address register (ad-
dress 00D816) are compared with address data. When this bit is set
to “1,” the 10-bit addressing format is selected and all the bits of the
2
When ESO = “0,” the following is performed.
I C address register are compared with the address data.
2
• PIN = “1,” BB = “0” and AL = “0” are set (they are bits of the I C
status register at address 00D916 ).
(5) Bits 6 and 7: connection control bits between
I2C-BUS interface and ports
(BSEL0, BSEL1)
2
• Writing data to the I C data shift register (address 00D716) is dis-
abled.
These bits control the connection between SCL and ports or SDA
and ports (refer to Figure 8.6.5).
“0”
“1” BSEL0
SCL1/P1
SCL2/P1
1
2
“0”
“1” BSEL1
SCL
Multi-master
I2C-BUS
“0”
“1” BSEL0
interface
SDA1/P1
SDA2/P1
3
4
“0”
“1” BSEL1
SDA
Note: Set the corresponding direction register to “1” to use the
2
port as multi-master I C-BUS interface.
Fig. 8.6.5 Connection Port Control by BSEL0 and BSEL1
Rev.1.00 Oct 01, 2002 page 35 of 110
REJ03B0134-0100Z
RENESAS [ RENESAS TECHNOLOGY CORP ]
