M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
2
8.6.1 I C Data Shift Register
2
The I C data shift register (S0 : address 00D716) is an 8-bit shift
register to store receive data and write transmit data.
When transmit data is written into this register, it is transferred to the
outside from bit 7 in synchronization with the SCL clock, and each
time one-bit data is output, the data of this register are shifted one bit
to the left. When data is received, it is input to this register from bit 0
in synchronization with the SCL clock, and each time one-bit data is
input, the data of this register are shifted one bit to the left.
2
The I C data shift register is in a write enable status only when the
2
ESO bit of the I C control register (address 00DA16) is “1.” The bit
2
counter is reset by a write instruction to the I C data shift register.
2
When both the ESO bit and the MST bit of the I C status register
(address 00D916) are “1,” the SCL is output by a write instruction to
2
2
the I C data shift register. Reading data from the I C data shift regis-
ter is always enabled regardless of the ESO bit value.
Note: To write data into the I2C data shift register after setting the MST bit to
“0” (slave mode), keep an interval of 8 machine cycles or more.
2
I C Data Shift Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C data shift register (S0) [Address 00D716
]
B
Name
Functions
After reset
R
R
W
W
0
to
7
This is an 8-bit shift register to store
receive data and write transmit data.
Indeterminate
D0 to D7
2
Note:
To write data into the I C data shift register after setting the MST bit to
“0” (slave mode), keep an interval of 8 machine cycles or more.
Fig. 8.6.2 Data Shift Register
Rev.1.00 Oct 01, 2002 page 32 of 110
REJ03B0134-0100Z
RENESAS [ RENESAS TECHNOLOGY CORP ]
