M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
2
2
8.6 MULTI-MASTER I C-BUS INTERFACE
Table 8.6.1 Multi-master I C-BUS Interface Functions
2
The multi-master I C-BUS interface is a serial communications cir-
Item
Function
2
cuit, conforming to the Philips I C-BUS data transfer format. This
2
In conformity with Philips I C-BUS
standard:
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
interface, offering both arbitration lost detection and a synchronous
functions, is useful for the multi-master serial communications.
Format
2
Figure 8.6.1 shows a block diagram of the multi-master I C-BUS in-
2
terface and Table 8.6.1 shows multi-master I C-BUS interface func-
2
tions.
In conformity with Philips I C-BUS
standard:
2
2
This multi-master I C-BUS interface consists of the I C address reg-
Master transmission
Master reception
Slave transmission
Slave reception
2
2
2
ister, the I C data shift register, the I C clock control register, the I C
Communication mode
2
control register, the I C status register and other control circuits.
SCL clock frequency 16.1 kHz to 400 kHz (at φ = 4 MHz)
φ : System clock = f(XIN)/2
Note : We are not responsible for any third party’s infringement of patent rights
or other rights attributable to the use of the control function (bits 6 and 7
of the I2C control register at address 00DA16) for connections between
the I2C-BUS interface and ports (SCL1, SCL2, SDA1, SDA2).
I2C address register (S0D)
b7
b0
Interrupt
generating
circuit
Interrupt
request signal
(IICIRQ)
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
Address comparator
Serial
data
(SDA)
Noise
elimination
circuit
Data
control
circuit
b7
b0
I2C data shift register
b7
b0
S0
AL AAS AD0 LRB
MST TRX BB PIN
I2C status
AL
register (S1)
circuit
Internal data bus
BB
circuit
Noise
elimination
circuit
Serial
clock
(SCL)
Clock
control
circuit
b7
b0
b7
BSEL1 BSEL0
b0
FAST
MODE
10BIT
SAD
ACK
BIT
ALS
CCR4 CCR3 CCR2 CCR1 CCR0
ACK
ESO BC2 BC1 BC0
I2C control register (S1D)
System clock (φ)
I2C clock control register (S2)
Clock division
Bit counter
2
Fig. 8.6.1 Block Diagram of Multi-master I C-BUS Interface
Rev.1.00 Oct 01, 2002 page 31 of 110
REJ03B0134-0100Z
RENESAS [ RENESAS TECHNOLOGY CORP ]
