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M37221EASP 参数 Datasheet PDF下载

M37221EASP图片预览
型号: M37221EASP
PDF下载: 下载PDF文件 查看货源
内容描述: 单片8位微机的CMOS电压合成器与屏幕上的显示控制器 [SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER]
分类和应用: 显示控制器计算机
文件页数/大小: 112 页 / 1165 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP  
8.6.6 START Condition Generation Method  
I2C statusregiste  
write signal  
2
When the ESO bit of the I C control register (address 00DA16) is “1,”  
2
execute a write instruction to the I C status register (address 00D916)  
SCL  
SDA  
to set the MST, TRX and BB bits to “1.” A START condition will then  
be generated. After that, the bit counter becomes “0002” and an SCL  
is output for 1 byte . The START condition generation timing and BB  
bit set timing are different in the standard clock mode and the high-  
speed clock mode. Refer to Figure 8.6.9 for the START condition  
generation timing diagram, and Table 8.6.2 for the START condition/  
STOP condition generation timing table.  
Setup  
time  
Hold time  
Set time for  
BB flag  
BB flag  
Setup  
time  
Fig. 8.6.9 START Condition Generation Timing Diagram  
8.6.7 STOP Condition Generation Method  
I2Cstatusregister  
writesignal  
2
When the ESO bit of the I C control register (address 00DA16) is “1,”  
2
execute a write instruction to the I C status register (address 00D916)  
SCL  
to set the MST bit and the TRX bit to “1” and the BB bit to “0”. A STOP  
condition will then be generated. The STOP condition generation tim-  
ing and the BB flag reset timing are different in the standard clock  
mode and the high-speed clock mode. Refer to Figure 8.6.10 for the  
STOP condition generation timing diagram, and Table 8.6.2 for the  
START condition/STOP condition generation timing table.  
Setup  
time  
Hold time  
SDA  
BB flag  
Reset time for  
BB flag  
Fig. 8.6.10 STOP Condition Generation Timing Diagram  
Table 8.6.2 START Condition/STOP Condition Generation Tim-  
ing Table  
Item  
Standard Clock Mode High-speed Clock Mode  
Setup time  
5.0 µs (20 cycles)  
2.5 µs (10 cycles)  
(START condition)  
Setup time  
4.25 µs (17 cycles)  
5.0 µs (20 cycles)  
3.0 µs (12 cycles)  
1.75 µs (7 cycles)  
2.5 µs (10 cycles)  
1.5 µs (6 cycles)  
(STOP condition)  
Hold time  
Set/reset time  
for BB flag  
Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the  
number of φ cycles.  
Rev.1.00 Oct 01, 2002 page 39 of 110  
REJ03B0134-0100Z  
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