M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
8.4 TIMERS
At reset, timers 3 and 4 are connected by hardware and “FF16” is
automatically set in timer 3; “0716” in timer 4. The f(XIN)/16 is se-
lected as the timer 3 count source. The internal reset is released by
timer 4 overflow in this state and the internal clock is connected.
At execution of the STP instruction, timers 3 and 4 are connected by
hardware and “FF16” is automatically set in timer 3; “0716” in timer 4.
However, the f(XIN)/16 is not selected as the timer 3 count source.
So set both bit 0 of timer 34 mode register (address 00F516) and bit
6 at address 00C716 to “0” before execution of the STP instruction
(f(XIN)/16 is selected as the timer 3 count source). The internal STP
state is released by timer 4 overflow in this state and the internal
clock is connected.
This microcomputer has 4 timers: timers 1 to 4. All timers are 8-bit
timers with the 8-bit timer latch. The timer block diagram is shown in
Figure 8.4.3.
All of the timers count down and their divide ratio is 1/(n+1), where n
is the value of timer latch. By writing a count value to the correspond-
ing timer latch (addresses 00F016 to 00F316 : timers 1 to 4), the value
is also set to a timer, simultaneously.
The count value is decremented by 1. The timer interrupt request bit
is set to “1” by a timer overflow at the next count pulse, after the
count value reaches “0016.”
8.4.1 Timer 1
Timer 1 can select one of the following count sources:
As a result of the above procedure, the program can start under a
stable clock.
• f(XIN)/16
• f(XIN)/4096
The timer-related registers is shown in Figures 8.4.1 and 8.4.2.
The count source of timer 1 is selected by setting bit 0 of timer 12
mode register 1 (address 00F416).
Timer interrupt request occurs at timer 1 overflow.
8.4.2 Timer 2
Timer 2 can select one of the following count sources:
• f(XIN)/16
• Timer 1 overflow signal
• External clock from the TIM2 pin
The count source of timer 2 is selected by setting bits 4 and 1 of
timer 12 mode register (address 00F416). When timer 1 overflow
signal is a count source for the timer 2, the timer 1 functions as an 8-
bit prescaler.
Timer 2 interrupt request occurs at timer 2 overflow.
8.4.3 Timer 3
Timer 3 can select one of the following count sources:
• f(XIN)/16
• External clock from the HSYNC pin
• External clock from the TIM3 pin
The count source of timer 3 is selected by setting bits 5 and 0 of
timer 34 mode register (address 00F516).
Timer 3 interrupt request occurs at timer 3 overflow.
8.4.4 Timer 4
Timer 4 can select one of the following count sources:
• f(XIN)/16
• f(XIN)/2
• Timer 3 overflow signal
The count source of timer 3 is selected by setting bits 1 and 4 of
timer 34 mode register (address 00F516). When timer 3 overflow
signal is a count source for the timer 4, the timer 3 functions as an 8-
bit prescaler.
Timer 4 interrupt request occurs at timer 4 overflow.
Rev.1.00 Oct 01, 2002 page 24 of 110
REJ03B0134-0100Z
RENESAS [ RENESAS TECHNOLOGY CORP ]
