M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
(4) Serial I/O interrupt
This is an interrupt request from the clock synchronous serial I/O
function.
Interrupt request bit
Interrupt enable bit
(5) f(XIN)/4096 interrupt
The f (XIN)/4096 interrupt occurs regularly with a f(XIN)/4096 pe-
riod. Set bit 0 of PWM output control register 1 to “0.”
Interrupt disable flag I
2
(6) Multi-master I C-BUS interface interrupt
2
This is an interrupt request related to the multi-master I C-BUS
Interrupt
request
BRK instruction
Reset
interface.
(7) BRK instruction interrupt
This software interrupt has the least significant priority. It does
not have a corresponding interrupt enable bit, and it is not af-
fected by the interrupt disable flag I (non-maskable).
Fig. 8.3.1 Interrupt Control
Rev.1.00 Oct 01, 2002 page 20 of 110
REJ03B0134-0100Z
RENESAS [ RENESAS TECHNOLOGY CORP ]
