M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
8.5 SERIAL I/O
The operation of the serial I/O is described below. The operation of
the serial I/O differs depending on the clock source; external clock or
internal clock.
This microcomputer has a built-in serial I/O which can either transmit
or receive 8-bit data serially in the clock synchronous mode.
The serial I/O block diagram is shown in Figure 8.5.1. The synchro-
nous clock I/O pin (SCLK), data output pin (SOUT), and data input pin
(SIN) also functions as port P2.
Bit 3 of the serial I/O mode register (address 00DC16) selects whether
the synchronous clock is supplied internally or externally (from the
SCLK pin). When an internal clock is selected, bits 1 and 0 select
whether f(XIN) or f(XCIN) is divided by 4, 16, 32, or 64. To use SIN pin
for serial I/O, set the corresponding bit of the port P2 direction regis-
ter (address 00C516) to “0.”
Data bus
Frequency
divider
XIN
1/2
1/2
1/4 1/8 1/16
SM1
Selection gate :
Connected to black
SM2
SM0
S
Synchronization circuit
colored side at reset.
SM : Serial I/O mode register
P20 latch
Serial I/O interrupt
request
S
CLK
Serial I/O counter (8)
MSB
SM3
P2
1
latch
SM5 : LSB
S
OUT(/IN)
SM3
(See note)
Serial I/O shift register (8)
(Address 00DD16
SIN
SM6
)
8
Note : When the data is set in the serial I/O register (address 00DD16), the register functions as the serial I/O shift register.
Fig. 8.5.1 Serial I/O Block Diagram
Rev.1.00 Oct 01, 2002 page 27 of 110
REJ03B0134-0100Z
RENESAS [ RENESAS TECHNOLOGY CORP ]
