M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
Timer 12 Mode Register
b7b6 b5b4b3 b2b1b0
0
Timer mode register (T12M) [Address 00F416
]
Name
Functions
0: f(XIN)/16
1: f(XIN)/4096
After reset R W
B
0
Timer 1 count source
selection bit 1 (T12M0)
R W
0
1
2
3
4
Timer 2 count source 0: Interrupt clock source
selection bit (T12M1) 1: External clock from TIM2 pin
R W
R W
R W
R W
0
0
0
0
0: Count start
1: Count stop
Timer 1 count
stop bit (T12M2)
Timer 2 count stop bit 0: Count start
(T12M3)
1: Count stop
0: f(XIN)/16
1: Timer 1 overflow
Timer 2 internal count
source selection bit 2
(T12M4)
5
Fix this bit to “0.”
R W
R —
0
0
6, 7 Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
Fig. 8.4.1 Timer 12 Mode Register
Timer 34 Mode Register
b7b6 b5b4b3 b2b1b0
Timer 34 mode register (T34M) [Address 00F516
]
B
0
Name
Functions
0 : f(XIN)/16
1 : External clock source
After reset R W
Timer 3 count source
selection bit (T34M0)
0
R W
1
Timer 4 internal
interrupt count source 1 : f(XIN)/16
selection bit (T34M1)
0 : Timer 3 overflow signal
0
R W
Timer 3 count stop bit
0: Count start
2
3
0
0
R W
R W
(T34M2)
1: Count stop
Timer 4 count stop bit
(T34M3)
0: Count start
1: Count stop
Timer 4 count source
selection bit (T34M4)
4
5
0: Internal clock source
1: f(XIN)/2
0
0
R W
R W
Timer 3 external count 0: TIM3 pin input
source selection bit
(T34M5)
1: HSYNC pin input
6, 7 Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
0
R —
Fig. 8.4.2 Timer 34 Mode Register
Rev.1.00 Oct 01, 2002 page 25 of 110
REJ03B0134-0100Z
RENESAS [ RENESAS TECHNOLOGY CORP ]
