M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
8.3 INTERRUPTS
8.3.1 Interrupt Causes
Interrupts can be caused by 14 different sources comprising 4 exter-
nal, 8 internal, 1 software, and 1 reset interrupts. Interrupts are vec-
tored interrupts with priorities as shown in Table 8.3.1. Reset is also
included in the table as its operation is similar to an interrupt.
When an interrupt is accepted,
(1) VSYNC, OSD interrupts
The VSYNC interrupt is an interrupt request synchronized with
the vertical sync signal.
The OSD interrupt occurs after character block display to the
CRT is completed.
■ The contents of the program counter and processor status regis-
ter are automatically stored into the stack.
(2) INT1 to INT3 external interrupts
The INT1 to INT3 interrupts are external interrupt inputs, the sys-
tem detects that the level of a pin changes from LOW to HIGH or
from HIGH to LOW, and generates an interrupt request. The in-
put active edge can be selected by bits 3 to 5 of the interrupt
input polarity register (address 00F916) : when this bit is “0,” a
change from LOW to HIGH is detected; when it is “1,” a change
from HIGH to LOW is detected. Note that both bits are cleared to
“0” at reset.
■ The interrupt disable flag I is set to “1” and the corresponding
interrupt request bit is set to “0.”
■ The jump destination address stored in the vector address enters
the program counter.
Other interrupts are disabled when the interrupt disable flag is set to
“1.”
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit. The interrupt request bits are
in Interrupt Request Registers 1 and 2 and the interrupt enable bits
are in Interrupt Control Registers 1 and 2. Figures 8.3.2 to 8.3.6 show
the interrupt-related registers.
(3) Timers 1 to 4 interrupts
An interrupt is generated by an overflow of timers 1 to 4.
Interrupts other than the BRK instruction interrupt and reset are ac-
cepted when the interrupt enable bit is “1,” interrupt request bit is "1,"
and the interrupt disable flag is “0.”
The interrupt request bit can be set to "0" by a program, but not set to
"1." The interrupt enable bit can be set to “0” and “1” by a program.
Reset is treated as a non-maskable interrupt with the highest priority.
Figure 8.3.1 shows interrupt controls.
Table 8.3.1 Interrupt Vector Addresses and Priority
Priority
Interrupt Source
Vector Addresses
Remarks
1
2
Reset
FFFF16, FFFE16
FFFD16, FFFC16
FFFB16, FFFA16
FFF916, FFF816
FFF516, FFF416
FFF316, FFF216
FFF116, FFF016
FFEF16, FFEE16
FFED16, FFEC16
FFEB16, FFEA16
FFE916, FFE816
FFE716, FFE616
FFE516, FFE416
FFDF16, FFDE16
Non-maskable
OSD interrupt
3
INT2 external interrupt
INT1 external interrupt
Timer 4 interrupt
Active edge selectable
Active edge selectable
4
5
6
f(XIN)/4096 interrupt
VSYNC interrupt
7
8
Timer 3 interrupt
9
Timer 2 interrupt
10
11
12
13
14
Timer 1 interrupt
Serial I/O interrupt
2
Multi-master I C-BUS interface interrupt
INT3 external interrupt
BRK instruction interrupt
Active edge selectable
Non-maskable
Rev.1.00 Oct 01, 2002 page 19 of 110
REJ03B0134-0100Z
RENESAS [ RENESAS TECHNOLOGY CORP ]
