M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
■ 2 page register area (addresses 21716 to 21B16)
<Bit allocation>
State immediately after reset>
:
: “0” immediately after reset
0
1
?
Function bit
:
Name
: “1” immediately after reset
: No function bit
: Indeterminate immediately
after reset
: Fix to this bit to “0”
(do not write to “1”)
0
1
: Fix to this bit to “1”
(do not write to “0”)
Bit allocation
State immediately after reset
b0 b7
Address
Register
b7
b0
0016
0016
0016
0016
0016
ROM correction address 1 (high-order)
ROM correction address 1 (low-order)
ROM correction address 2 (high-order)
ROM correction address 2 (low-order)
ROM correction enable register (RCR)
21716
21816
21916
21A16
21B16
RCR1 RCR0
0
0
Note: Only M37221M4H/M6H/M8H/MAH-XXXSP/FP and M37221EASP/FP have 2 pag.e register.
Fig. 8.2.5 Memory Map of 2 Page Register Area
Rev.1.00 Oct 01, 2002 page 17 of 110
REJ03B0134-0100Z
RENESAS [ RENESAS TECHNOLOGY CORP ]
