M37161M8/MA/MF-XXXSP/FP,M37161EFSP/FP
8.
FUNCTION BLOCK
DESCRIPTION
8.1 CENTRAL PROCESSING UNIT (CPU)
This microcomputer uses the standard 740 Family instruction set.
Refer to the table of 740 Family addressing modes and machine
instructions or the SERIES 740 <Software> User’s Manual for de-
tails on the instruction set.
Availability of 740 Family instructions are as follows:
The FST, SLW instruction cannot be used.
The MUL, DIV, WIT and STP instructions can be used.
8.1.1 CPU Mode Register
The CPU mode register includes a stack page selection bit and inter-
nal system clock selection bit. The CPU mode register is allocated at
address 00FB
16
.
CPU Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
1 1
0 0
CPU mode register (CM) [Address 00FB
16
]
Name
0, 1 Processor mode bits
(CM0, CM1)
B
Functions
b1 b0
After reset R W
0
R W
2
Stack page selection
bit (CM2) (See note1)
0: Single-chip mode
1:
0:
Not available
1:
0: 0 page
1: 1 page
0
0
1
1
1
1
RW
R W
R W
RW
3, 4 Fix these bits to “1.”
5 X
COUT
drivability
selection bit (CM5)
6 Main Clock (X
IN
-X
OUT
)
stop bit (CM6)
7 Internal system clock
selection bit
(CM7)
0: LOW drive
1: HIGH drive
0: Oscillating
1: Stopped
0: X
IN
-X
OUT
selected
(high-speed mode)
1: X
CIN
–X
COUT
selected
(low-speed mode)
1
0
0
RW
Note 1:
This bit is set to “1” after the reset release.
Fig. 8.1.1 CPU Mode Register
Rev.1.00
2003.11.25
page 11 of 128
RENESAS [ RENESAS TECHNOLOGY CORP ]
