MULTIJUNCTION TIMERS
10.3 TOP (Output-Related 16-Bit Timer)
10
In the example below, the counter and the reload register are initially set to H’A000 and H’E000, respectively.
When the timer is enabled, the counter starts counting down and when it underflows after reaching the
minimum count, the counter is loaded with the content of the reload register and continues counting down.
Enabled
Underflow
(first time)
Underflow
(second time)
(by writing to the enable bit
or by external input)
Count clock
Enable bit
H'FFFF
H'(E000-1)
H'FFFF
H'(E000-1)
H'FFFF
H'E000
Count down from the
counter's set value
Count down from the
reload register's
set value
Count down from the
reload register's
set value
H'A000
Counter
H'0000
H'E000
Reload register
(Unused)
Correction register
F/F output
Data inverted by
enable
Data inverted
by underflow
Data inverted
by underflow
TOP interrupt request
due to underflow
Note: • This diagram does not show detailed timing information.
Figure 10.3.18 Typical Operation in TOP Continuous Output Mode
32180 Group User’s Manual (Rev.1.0)
10-92
RENESAS [ RENESAS TECHNOLOGY CORP ]
