MULTIJUNCTION TIMERS
10.3 TOP (Output-Related 16-Bit Timer)
10
(3) Precautions on using TOP delayed single-shot output mode
The following describes precautions to be observed when using TOP delayed single-shot output mode.
• If the counter stops due to an underflow in the same clock period as the timer is enabled by external input,
the former has priority so that the counter stops.
• If the counter stops due to an underflow in the same clock period as count is enabled by writing to the enable
bit, the latter has priority so that count is enabled.
• If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable
bit, the latter has priority so that count is disabled.
• Even if the counter overflows due to correction of counts, no interrupt requests are generated for reasons of
an overflow. Therefore, if the counter underflows in the subsequent down-count after an overflow, a false
interrupt request is generated for an underflow that includes the overflowed count.
• If the counter is accessed for read immediately after being reloaded pursuant to an underflow, the counter
value temporarily reads as H’FFFF but immediately changes to (reload value – 1) at the next clock edge.
Reload due to underflow
Count clock
Enable bit
"H"
Count down from the
reload register value
Reload cycle
Counter value
Reload register
H'0001
H'0000
H'FFFF
H'AAA9
H'AAA8
H'(AAAA-1)
H'(AAAA-2)
H'AAAA
What is seen during reload cycle is always H'FFFF,
and not the reload register value (in this case, H'AAAA).
Figure 10.3.16 Counter Value Immediately after Underflow
32180 Group User’s Manual (Rev.1.0)
10-90
RENESAS [ RENESAS TECHNOLOGY CORP ]
