MULTIJUNCTION TIMERS
10.4 TIO (Input/Output-Related 16-Bit Timer)
10
10.4.2 Outline of Each Mode of TIO
Each mode of TIO is outlined below. For each TIO channel, only one of the following modes can be selected.
(1) Measure clear/free-run input modes
In measure clear/free-run input modes, the timer is used to measure a duration of time from when the counter
starts counting till when an external capture signal is entered.
After the timer is enabled (by writing to the enable bit in software), the counter starts counting down synchro-
nously with the count clock. When a capture signal is entered from an external device, the counter value at
that point in time is written into a register called the “measure register.”
In measure clear input mode, the counter value is initialized to H’FFFF upon capture, from which the counter
starts counting down again. In measure free-run input mode, the counter continues counting down even after
capture and upon underflow, recycles to H’FFFF, from which it starts counting down again.
To stop the counter, disable count by writing to the enable bit in software. An interrupt request can be gener-
ated by a counter underflow or execution of a measure operation.
(2) Noise processing input mode
In noise processing input mode, the timer is used to detect that the input signal remained in the same state for
over a predetermined time.
In noise processing input mode, a high or low level on external input activates the counter and if the input
signal remains in the same state for over a predetermined time before the counter underflows, the counter
generates an interrupt request before stopping. If the valid-level signal being applied turns to an invalid level
before the counter underflows, the counter temporarily stops counting and when a valid-level signal is en-
tered again, the counter is reloaded with the initial count and restarts counting.
The timer stops at the same time the counter underflows or count is disabled by writing to the enable bit. An
interrupt request can be generated by a counter underflow.
(3) PWM output mode (without correction function)
In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle.
When the timer is enabled (by writing to the enable bit in software or by external input) after setting the initial
values in the reload 0 and reload 1 registers, the counter is loaded with the reload 0 register value and starts
counting down synchronously with the count clock. The first time the counter underflows, it is loaded with the
reload 1 register value and continues counting. Thereafter, the counter is loaded with the reload 0 and reload
1 register values alternately each time an underflow occurs.
The F/F output waveform in PWM output mode is inverted when the counter starts counting and each time it
underflows. The timer stops at the same time count is disabled by writing to the enable bit (and not in
synchronism with PWM output period). An interrupt request can be generated when the counter underflows
every other time (second time, fourth time and so on) after being enabled.
32180 Group User’s Manual (Rev.1.0)
10-96
RENESAS [ RENESAS TECHNOLOGY CORP ]
