MULTIJUNCTION TIMERS
10.3 TOP (Output-Related 16-Bit Timer)
10
In the example below, the counter and the reload register are initially set to H’A000 and H’F000, respectively.
When the timer is enabled, the counter starts counting down and when it underflows after reaching the
minimum count, the counter is loaded with the content of the reload register and continues counting down. In
the diagram below, the value H’0008 is written to the correction register when the counter has counted down
to H’9000. As a result of this correction, the counter has its count value increased to H’9008 and counts
(H’F000 + 1 + H’0008 + 1) after the first underflow before it stops.
Enabled
Underflow
(first time)
Underflow
(second time)
(by writing to the enable bit
or by external input)
Count clock
Enable bit
Write to the
correction register
H'FFFF
H'(F000+0008+1)
H'F000
H'9000+H'0008
H'9000
Counter
H'A000
H'0000
Reload register
H'F000
Correction register
F/F output
Undefined
H'0008
Data inverted
by underflow
Data inverted
by underflow
TOP interrupt request
due to underflow
Note: • This diagram does not show detailed timing information.
Figure 10.3.15 Typical Operation in TOP Delayed Single-shot Output Mode when Count is Corrected
32180 Group User’s Manual (Rev.1.0)
10-89
RENESAS [ RENESAS TECHNOLOGY CORP ]
